u-boot.git/arch/arm/include/asm/system.h, branch v2025.01

CONFIG_SYS_NONCACHED_MEMORY: Move prototypes to include/cpu_func.h for consistency

2024-10-29T22:17:18Z

Currently, a number of generic cache related functions have their common prototype declared in include/cpu_func.h. Move the current set of noncached functions there as well to match. Signed-off-by: Tom Rini

arm: Implement read_mpidr on armv7

2024-10-27T23:24:13Z

Implement read_mpidr() on armv7 to make use of it in generic code that compiles on both armv7 and armv8. Signed-off-by: Patrick Rudolph Reviewed-by: Simon Glass

armv8: mmu: add a way to map additional regions

2024-09-06T08:47:46Z

In some cases we might want to map some memory region after enabling caches. Introduce a new helper for this. Reviewed-by: Neil Armstrong Signed-off-by: Caleb Connolly

armv8: generic_timer: Use event stream for udelay

2024-05-13T22:51:14Z

Polling cntpct_el0 in a tight loop for delays is inefficient. This is particularly apparent on Arm FVPs, which do not simulate real time, meaning that a 1s sleep can take a couple of orders of magnitude longer to execute in wall time. If running at EL2 or above (where CNTHCTL_EL2 is available), enable the cntpct_el0 event stream temporarily and use wfe to implement the delay more efficiently. The event period is chosen as a trade-off between efficiency and the fact that Arm FVPs do not typically simulate real time. This is only implemented for Armv8 boards, where an architectural timer exists, and only enabled by default for the ARCH_VEXPRESS64 board family. Signed-off-by: Peter Hoyes Reviewed-by: Andre Przywara

arm: Move sev() and wfe() definitions to common Arm header file

2024-05-13T22:51:14Z

The sev() and wfe() asm macros are currently defined only for mach-exynos. As these are common Arm instructions, move them to the common asm/system.h header file, for both Armv7 and Armv8, so they can be used by other machines. wfe may theoretically trigger a context switch if an interrupt occurs so add a memory barrier to this call. Signed-off-by: Peter Hoyes Reviewed-by: Andre Przywara

arm: caches: Make DCACHE_DEFAULT_OPTION accessible for ARM64 arch

2023-11-13T09:55:38Z

This fixes the following compilation error in ARM64: arch/arm/mach-stm32mp/dram_init.c: In function ‘board_get_usable_ram_top’: arch/arm/mach-stm32mp/dram_init.c:59:45: error: ‘DCACHE_DEFAULT_OPTION’ undeclared (first use in this function) 59 | mmu_set_region_dcache_behaviour(reg, size, DCACHE_DEFAULT_OPTION); | ^~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay

driver: rng: Add DM_RNG interface for ARMv8.5 RNDR registers

2023-10-11T17:22:32Z

The ARMv8.5 architecture extension defines architectural RNDR/RNDRRS system registers, that provide 64 bits worth of randomness on every read. Since it's an extension, and implementing it is optional, there is a field in the ID_AA64ISAR0_EL1 ID register to query the availability of those registers. Add a UCLASS_RNG driver that returns entropy via repeated reads from those system registers, if the extension is implemented. The driver always binds, but checks the availability in the probe() routine. This helps systems which suffer from low boot entropy, since U-Boot can provide entropy via the generic UEFI entropy gathering protocol to the OS, at an early stage. Signed-off-by: Andre Przywara Reviewed-by: Simon Glass

armv8: Always unmask SErrors

2022-03-02T18:59:29Z

The ARMv8 architecture describes the "SError interrupt" as the fourth kind of exception, next to synchronous exceptions, IRQs, and FIQs. Those SErrors signal exceptional conditions from which the system might not easily recover, and are normally generated by the interconnect as a response to some bus error. A typical situation is access to a non-existing memory address or device, but it might be deliberately triggered by a device as well. The SError interrupt replaces the Armv7 asynchronous abort. Trusted Firmware enters U-Boot (BL33) typically with SErrors masked, and we never enable them. However any SError condition still triggers the SError interrupt, and this condition stays pending, it just won't be handled. If now later on the Linux kernel unmasks the "A" bit in PState, it will immediately take the exception, leading to a kernel crash. This leaves many people scratching their head about the reason for this, and leads to long debug sessions, possibly looking at the wrong places (the kernel, but not U-Boot). To avoid the situation, just unmask SErrors early in the ARMv8 boot process, so that the U-Boot exception handlers reports them in a timely manner. As SErrors are typically asynchronous, the register dump does not need to point at the actual culprit, but it should happen very shortly after the condition. For those exceptions to be taken, we also need to route them to EL2, if U-Boot is running in this exception level. This removes the respective code snippet from the Freescale lowlevel routine, as this is now handled in generic ARMv8 code. Reported-by: Nishanth Menon Signed-off-by: Andre Przywara

Revert most of the series for adding vexpress_aemv8r support

2021-09-03T14:42:15Z

Per a request from Andre Przywara and agreed with by Peter Hoyes, the vexpress aemv8r support wasn't quite ready to be merged, but the discussion had moved off list. We should keep the first patch in the series for now, but revert the rest. This reverts the following commits: e0bd6f31ce41 doc: Add documentation for the Arm vexpress board configs 30e5a449e8c7 arm: Use armv8_switch_to_el1 env to switch to EL1 b53bbca63bf4 vexpress64: Add BASER_FVP vexpress board variant 2f5b7b74903f armv8: Add ARMv8 MPU configuration logic 37a757e227cc armv8: Ensure EL1&0 VMSA is enabled Signed-off-by: Tom Rini

psci: fix double declaration

2021-09-02T15:19:58Z

The prototype of psci_features() duplicated. Remove extra declaration. Fixed: e21e3ffdd1 ("psci: Fix warnings when compiling with W=1") Reported-by: Michael Scott Signed-off-by: Oleksandr Suvorov