u-boot.git/arch/arm/include/asm, branch v2013.10

Coding Style cleanup: remove trailing white space

2013-10-14T20:06:53Z

Signed-off-by: Wolfgang Denk

ARM: omap4-panda: Add MAC address creation for panda

2013-10-14T20:06:53Z

Add a MAC address create based on the OMAP die ID registers. Then poplulate the ethaddr enviroment variable so that the device tree alias can be updated prior to boot. Signed-off-by: Dan Murphy

Merge branch 'master' of git://git.denx.de/u-boot-arm

2013-10-08T13:51:48Z

spi: exynos: Support word transfers

2013-10-08T12:48:12Z

Since SPI register access is so expensive, it is worth transferring data a word at a time if we can. This complicates the driver unfortunately. Use the byte-swapping feature to avoid having to convert to/from big endian in software. This change increases speed from about 2MB/s to about 4.5MB/s. Signed-off-by: Simon Glass Signed-off-by: Rajeshwari S Shinde Reviewed-by: Jagannadha Sutradharudu Teki

socfpga: Adding System Manager driver

2013-10-07T17:32:21Z

Adding System Manager driver which will configure the pin mux for real hardware Cyclone V development kit (not Virtual Platform) Signed-off-by: Chin Liang See Reviewed-by: Pavel Machek Acked-by: Dinh Nguyen Cc: Wolfgang Denk CC: Pavel Machek Cc: Dinh Nguyen Cc: Tom Rini Cc: Albert Aribaud

omap5: add qspi support

2013-10-07T12:25:50Z

Add QSPI definitions and clock configuration support. Signed-off-by: Matt Porter Signed-off-by: Sourav Poddar Reviewed-by: Jagannadha Sutradharudu Teki

ARM: IGEP0033: Update timing to run DDR at 400MHz.

2013-10-07T11:43:46Z

We can run the DDR at 400MHz, so update the timings for that purpose. Signed-off-by: Enric Balletbo i Serra Reviewed-by: Javier Martinez Canillas

Merge branch 'master' of git://git.denx.de/u-boot-arm

2013-10-04T17:17:48Z

ARM: extend non-secure switch to also go into HYP mode

2013-10-03T19:28:55Z

For the KVM and XEN hypervisors to be usable, we need to enter the kernel in HYP mode. Now that we already are in non-secure state, HYP mode switching is within short reach. While doing the non-secure switch, we have to enable the HVC instruction and setup the HYP mode HVBAR (while still secure). The actual switch is done by dropping back from a HYP mode handler without actually leaving HYP mode, so we introduce a new handler routine in our new secure exception vector table. In the assembly switching routine we save and restore the banked LR and SP registers around the hypercall to do the actual HYP mode switch. The C routine first checks whether we are in HYP mode already and also whether the virtualization extensions are available. It also checks whether the HYP mode switch was finally successful. The bootm command part only calls the new function after the non-secure switch. Signed-off-by: Andre Przywara

ARM: add SMP support for non-secure switch

2013-10-03T19:28:51Z

Currently the non-secure switch is only done for the boot processor. To enable full SMP support, we have to switch all secondary cores into non-secure state also. So we add an entry point for secondary CPUs coming out of low-power state and make sure we put them into WFI again after having switched to non-secure state. For this we acknowledge and EOI the wake-up IPI, then go into WFI. Once being kicked out of it later, we sanity check that the start address has actually been changed (since another attempt to switch to non-secure would block the core) and jump to the new address. The actual CPU kick is done by sending an inter-processor interrupt via the GIC to all CPU interfaces except the requesting processor. The secondary cores will then setup their respective GIC CPU interface. While this approach is pretty universal across several ARMv7 boards, we make this function weak in case someone needs to tweak this for a specific board. The way of setting the secondary's start address is board specific, but mostly different only in the actual SMP pen address, so we also provide a weak default implementation and just depend on the proper address to be set in the config file. Signed-off-by: Andre Przywara