u-boot.git/arch/arm/include/asm, branch v2016.11

arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode

2016-11-13T20:54:36+00:00

While we setup the mmu initially we mark set_section_dcache with
DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro
is rightly defined with TTB_SECT_XN_MASK set so as to mark all the
4GB XN. In case of LPAE mode  XN(Execute-never) bit is not set with
DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which
keeps all the regions execute okay and this leads to random speculative
fetches in random memory regions which was eventually caught by kernel
omap-l3-noc driver.

Fix this to mark the regions as XN by default.

Signed-off-by: Keerthy 
Reviewed-by: Alexander Graf 
Reviewed-by: Tom Rini

armv8: add hooks for all cache-wide operations

2016-11-07T22:36:29+00:00

SoC-specific logic may be required for all forms of cache-wide
operations; invalidate and flush of both dcache and icache (note that
only 3 of the 4 possible combinations make sense, since the icache never
contains dirty lines). This patch adds an optional hook for all
implemented cache-wide operations, and renames the one existing hook to
better represent exactly which operation it is implementing. A dummy
no-op implementation of each hook is provided.

Signed-off-by: Stephen Warren 
Reviewed-by: Simon Glass 
Signed-off-by: Tom Warren

rk3288: sdram: auto-detect the capacity

2016-10-30T19:29:06+00:00

Add support for rk3288 dram capacity auto detect, support DDR3 and
LPDDR3, DDR2 is not supported.
The program will automatically detect:
- channel number
- rank number
- column address number
- row address number

The dts file do not need to describe those info after apply this patch.

Signed-off-by: Kever Yang 
Tested-by: Simon Glass 
Tested-by: Vagrant Cascadian 
Tested-by: Vagrant Cascadian

rockchip: rk3288: Move rockchip_get_cru() out of the driver

2016-10-30T19:29:06+00:00

This function is called from outside the driver. It should be placed into
common SoC code. Move it.

Signed-off-by: Simon Glass 
Reviewed-by: Kever Yang

rockchip: rk3399: Move rockchip_get_cru() out of the driver

2016-10-30T19:29:06+00:00

This function is called from outside the driver. It should be placed into
common SoC code. Move it.

Also rename the driver symbol to be more consistent with the other rockchip
clock drivers.

Signed-off-by: Simon Glass 
Reviewed-by: Kever Yang

rockchip: rk3036: Move rockchip_get_cru() out of the driver

2016-10-30T19:29:06+00:00

This function is called from outside the driver. It should be placed into
common SoC code. Move it.

Also rename the driver symbol to be more consistent with the other rockchip
clock drivers.

Signed-off-by: Simon Glass 
Reviewed-by: Kever Yang

sunxi: Add support for SID e-fuses on sun9i

2016-10-30T10:38:04+00:00

The A80 has SID e-fuses. Like other newer SoCs, the actual e-fuses
are at an offset of 0x200 within the SID address space.

Signed-off-by: Chen-Yu Tsai 
Acked-by: Hans de Goede 
Signed-off-by: Hans de Goede

sunxi: add initial clock setup for sun9i for SPL

2016-10-30T10:38:04+00:00

This is a cleaned up version set_pll() from Allwinner's boot0 source
(bootloader/basic_loader/bsp/bsp_for_a80/common/common.c).

[wens@csie.org: Added commit message; style cleanup]
Signed-off-by: Chen-Yu Tsai 
Acked-by: Hans de Goede 
Signed-off-by: Hans de Goede

sunxi: add gtbus-initialisation for sun9i

2016-10-30T10:38:04+00:00

On sun9i, the GTBUS manages transaction priority and bandwidth
for multiple read ports when accessing DRAM. The initialisation
mirrors the settings from Allwinner's boot0 for now, even though
this may not be optimal for all applications (e.g. headless
systems might want to give priority to IO modules).

Adding a common callout to gtbus_init() from the SPL clock init
with a weakly defined implementation in sunxi/clock.c to fallback
to for platforms that don't require this.

[wens@csie.org: Moved gtbus_sun9i.c to arch/arm/mach-sunxi/; style cleanup]
Signed-off-by: Chen-Yu Tsai 
Acked-by: Hans de Goede 
Signed-off-by: Hans de Goede

sunxi: DRAM initialisation for sun9i

2016-10-30T10:38:04+00:00

This adds DRAM initialisation code for sun9i, which calculates the
appropriate timings based on timing information for the supplied
DDR3 bin and the clock speeds used.

With this DRAM setup, we have verified DDR3 clocks of up to 792MHz
(i.e. DDR3-1600) on the A80-Q7 using a dual-channel configuration.

[wens@csie.org: Moved dram_sun9i.c to arch/arm/mach-sunxi/; style cleanup]
Signed-off-by: Chen-Yu Tsai 
[hdegoede@redhat.com: Drop some huge non-documenting #if 0 ... #endif blocks]
[hdegoede@redhat.com: Fix checkpatch warnings]
Signed-off-by: Hans de Goede