u-boot.git/arch/arm/include, branch next

Merge tag 'mediatek-for-next-2026-08-24' of https://git.u-boot-project.org/u-boot/custodians/u-boot-mediatek into next

2026-08-25T17:36:46Z

* New HDMI PHY and I2C DDC drivers, default EDID_ADDR macro * MT8189 clock qualifier fix * Phase-aware PSCI reset (MT8195/MT8365) * dwc_eth_qos MT8366 support * MediaTek TPHY v3 hardware support * mtk_snor mt8188/mt8189 compatible-string cleanup * MT6358/MT6366 PMIC regulator + pwrap support * MediaTek pinctrl Kconfig cleanup (per-SoC symbols → single driver + TARGET_*) * New MT8366 pinctrl driver + dt-bindings header * MediaTek serial driver clock-handling fixes

ARM: imx: Support detection of ECSPI recovery mode on i.MX6

2026-08-14T19:19:51Z

The i.MX6 allows to boot from a SPI NOR as a fallback if the primary boot fails. Parse the ROM log in order to detect this and return the proper boot device in spl_boot_device(). Otherwise the primary boot device is returned even if it was not used. To make imx6_is_ecspi_recovery_boot() usable in U-Boot proper, add them in arch/arm/mach-imx/init.c. This was tested on i.MX6S and the implementation covers other i.MX6 variants based on the documentation from NXP (AN12853). Assisted-by: Claude:claude-opus-5 Signed-off-by: Frieder Schrempf

edid: add default EDID_ADDR macro

2026-08-13T15:03:57Z

EDID info is most of the time stored at address 0x50, so define a macro for it in the common edid.h header. Also drop the now-duplicate definition from the Rockchip edp_rk3288.h header and rely on the common one. Signed-off-by: Julien Stephan Reviewed-by: Heiko Schocher Link: https://patch.msgid.link/20260727-mt8188-add-ddc-i2c-driver-v2-1-bf1c45fcd588@baylibre.com Signed-off-by: David Lechner

clk: rockchip: pll: fix overflow and drop manual two's complement on RK3588/RK3576

2026-08-12T14:55:03Z

The TRM defines the fractional PLL adjustment coefficient as a signed two's complement number, 16 bits wide, so store and use it as such to avoid confusion and enable proper signed arithmetics, promoting operands with automatic sign extension. This also fixes an overflow when the current rk3588_pll_get_rate calculates the fractional component in 32 bits before assigning it to a 64-bit holding variable, given that OSC_HZ is 24000000U and k can be from -32768 to 32767. Fixes: b851c006a150 ("clk: rockchip: pll: Add pll_rk3588 type for rk3588") Reviewed-by: Quentin Schulz Signed-off-by: Alexey Charkov Link: https://patch.msgid.link/20260723-rk3588-fracpll-v2-5-382d113f3a80@flipper.net Signed-off-by: Quentin Schulz

imx9{4, 5, 52}_evk: power on mcore according to SM config

2026-07-27T14:25:27Z

When working with SM config mx9{4,5,52}evkrpmsg, mcores are not booted by ROM. Hence, power on the mcore and initialize TCM ECC in u-boot for subsequent mcore booting. Signed-off-by: Ye Li [fabio: Adapted to mainline context] Signed-off-by: Fabio Estevam

imx9: bootaux: Support booting CM70, CM71 and CM33 sync cores

2026-07-27T14:25:22Z

Support booting CM70, CM71 and CM33 sync core image by bootaux command on iMX95, iMX94 and iMX952. (iMX95 and iMX952 only supports CM70). Each core uses different core id which is defined by SM and passed in SIP call. - CM33: 0 - CM70: 1 - CM71: 7 - CM33S: 8 Prior to run bootaux to start core, prepaux is needed before loading image. Below is example for booting CM70 TCM image on iMX95. =>fatload mmc 1:1 0x90000000 rpmsg.bin =>prepaux 1 =>cp.b 0x90000000 0x203c0000 ${filesize} =>bootaux 0 1 Signed-off-by: Alice Guo Signed-off-by: Ye Li Signed-off-by: Peng Fan Signed-off-by: Jacky Bai

imx9: bootaux: Support authenticate signed Mcore container image

2026-07-27T14:25:19Z

Add new command bootaux_cntr to replace bootaux in secure boot (CONFIG_AHAB_BOOT=y) to authenticate signed M33 core image. The M33 image must be packed in container format and signed. bootaux_cntr supports Mcore image loaded to TCM or run as FlexSPI NOR XIP. Signed-off-by: Ye Li [fabio: Adapted to use gd->dram[i]] Signed-off-by: Fabio Estevam

Merge patch series "arm: aspeed: add initial AST2700 SoC support"

2026-06-29T21:29:56Z

Ryan Chen says: AST2700 is the 8th generation of Integrated Remote Management Processor introduced by ASPEED Technology Inc. It is a Board Management Controller (BMC) SoC family with a dual-die architecture: SoC0 ("CPU" die with four ARM Cortex-A35 application cores) and SoC1 ("IO" die with peripherals) each SoC have its own SCU PLLs, clock dividers and reset domains. Link: https://lore.kernel.org/r/20260612-ast2700_clk-v4-0-9bea29cfdc39@aspeedtech.com

ram: aspeed: add SDRAM controller driver for AST2700

2026-06-29T19:43:21Z

Add a SDRAM controller driver for the AST2700, derived from the existing AST2700 controller code used by the Ibex SPL but adapted to run from ARM U-Boot proper on the Cortex-A35 cores. The DDR4/DDR5 controller and its DesignWare PHY are programmed by the Ibex SPL before ARM U-Boot proper takes over. This driver reads back the configuration left by the SPL, probes the controller, and exposes ram_info (base and size, with the VGA carve-out subtracted) via UCLASS_RAM so that dram_init() can populate gd->ram_size. The PHY firmware-load entry points (dwc_ddrphy_phyinit_userCustom_*) are kept compiled but call a __weak fmc_hdr_get_prebuilt() stub when ARM U-Boot proper is the caller; the real implementation is provided by the Ibex SPL via the same fmc_hdr.h descriptor format (here added for the ARM build). Adds the supporting register-layout headers under arch/arm/include/asm/arch-aspeed/: - sdram.h: SDRAM controller and DWC PHY register definitions - scu.h: SCU bits referenced by the SDRAM driver - fmc_hdr.h: prebuilt-blob descriptor (binary-compatible with arch/riscv/include/asm/arch-ast2700/fmc_hdr.h used by the Ibex SPL) Signed-off-by: Ryan Chen

arm: aspeed: add ASPEED AST2700 SoC family support

2026-06-29T19:43:20Z

Add initial support for the ASPEED AST2700, an arm64 (Cortex-A35) Baseboard Management Controller (BMC) SoC. AST2700 is Aspeed's 8th generation BMC and uses a dual-die architecture: SoC0 (the "CPU" die) hosts the four Cortex-A35 cores and its own SCU at 0x12c02000, while SoC1 (the "IO" die) hosts the peripherals and its own SCU at 0x14c02000. This commit adds: - ASPEED_AST2700 Kconfig option and the ast2700 mach subdir (mach Makefile, ast2700/Kconfig, board/aspeed/evb_ast2700/*) - arm64 MMU map covering the SoC device window and the DRAM region at 0x4_0000_0000 (up to 8 GiB) - lowlevel_init.S for early CPU bring-up - cpu-info: print SoC ID (AST2700/2720/2750 A0/A1/A2 variants) and reset cause (cold reset, EXT reset, WDT reset) - board_common: dram_init via UCLASS_RAM, AHBC timeout init - platform: env_get_location() that selects SPI/eMMC based on the IO-die HW strap; arch_misc_init() that exposes ${boot_device} and ${verify} to the boot script - SCU0/SCU1 register layout header (scu_ast2700.h) - configs/evb-ast2700_defconfig and include/configs/evb_ast2700.h for the AST2700 EVB board The defconfig depends on ast2700-evb.dts, which is introduced in a subsequent patch; this commit must be applied with the remaining series for evb-ast2700_defconfig to build. Signed-off-by: Ryan Chen