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<title>u-boot.git/arch/arm/include, branch v2014.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/include?h=v2014.04</id>
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<updated>2014-04-08T07:25:08Z</updated>
<entry>
<title>Merge branch 'u-boot/master' into 'u-boot-arm/master'</title>
<updated>2014-04-08T07:25:08Z</updated>
<author>
<name>Albert ARIBAUD</name>
<email>albert.u.boot@aribaud.net</email>
</author>
<published>2014-04-08T07:25:08Z</published>
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<id>urn:sha1:519fdde9e6a6ebce7dc743b4f5621503d25b7a45</id>
<content type='text'>
Conflicts:
	arch/arm/cpu/arm926ejs/mxs/Makefile
	include/configs/trats.h
	include/configs/trats2.h
	include/mmc.h
</content>
</entry>
<entry>
<title>arm64 patch: gicv3 support</title>
<updated>2014-04-07T22:15:12Z</updated>
<author>
<name>David Feng</name>
<email>fenghua@phytium.com.cn</email>
</author>
<published>2014-03-14T06:26:27Z</published>
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<id>urn:sha1:c71645ad2bd5179ad21e2501c26f574e9688f02a</id>
<content type='text'>
This patch add gicv3 support to uboot armv8 platform.

Changes for v2:
  - rename arm/cpu/armv8/gic.S with arm/lib/gic_64.S
  - move smp_kick_all_cpus() from gic.S to start.S, it would be
    implementation dependent.
  - Each core initialize it's own ReDistributor instead of master
    initializeing all ReDistributors. This is advised by arnab.basu
    &lt;arnab.basu@freescale.com&gt;.

Signed-off-by: David Feng &lt;fenghua@phytium.com.cn&gt;
</content>
</entry>
<entry>
<title>arm: vf610: add enet1 support</title>
<updated>2014-04-07T18:15:44Z</updated>
<author>
<name>Marcel Ziswiler</name>
<email>marcel@ziswiler.com</email>
</author>
<published>2014-03-11T17:43:59Z</published>
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<id>urn:sha1:6c81a93db700021614c6ae150f8c1c995173201f</id>
<content type='text'>
This patch contains several changes required for second Ethernet
(enet1/RMII1) port on vf610
- ANADIG PLL5 control definitions required for Ethernet RMII1 clock
- Secondary Ethernet (enet1) MAC RMII1 base address definition
- RMII1 iomux definitions
- VF610_PAD_PTA6__RMII0_CLKOUT iomux definition required for
  internal (e.g. crystal-less) Ethernet clocking.

Signed-off-by: Marcel Ziswiler &lt;marcel@ziswiler.com&gt;
[stefan@agner.ch: regrouped patch]
Signed-off-by: Stefan Agner &lt;stefan@agner.ch&gt;
</content>
</entry>
<entry>
<title>arm: vf610: add uart0 clock/iomux definitions</title>
<updated>2014-04-07T18:15:37Z</updated>
<author>
<name>Marcel Ziswiler</name>
<email>marcel@ziswiler.com</email>
</author>
<published>2014-03-11T17:43:58Z</published>
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<id>urn:sha1:c7098965e31b6faf1a861fcca77ef7112b9bf6e4</id>
<content type='text'>
Add CCM_CCGR0_UART0_CTRL_MASK clock definition and add TX/RX iomux
definitions for UART0 (aka. SCI0).

Signed-off-by: Marcel Ziswiler &lt;marcel@ziswiler.com&gt;
[stefan@agner.ch: regrouped patch]
Signed-off-by: Stefan Agner &lt;stefan@agner.ch&gt;
</content>
</entry>
<entry>
<title>arm: vf610: fix anadig register struct</title>
<updated>2014-04-07T18:15:29Z</updated>
<author>
<name>Marcel Ziswiler</name>
<email>marcel@ziswiler.com</email>
</author>
<published>2014-03-11T17:43:57Z</published>
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<id>urn:sha1:25839c01975b865f2e6a0dac056d207e9288a281</id>
<content type='text'>
The anadig_reg structure started at the wrong offset (fixed by adding
reserved_0x000[4]), was missing some reserved field required for
alignment purpose (reserved_0x094[3] between pll4_denom and pll6_ctrl)
and further contained a too short reserved field causing further miss-
alignment (reserved_0x0C4[7]). Also, rename all the reserved fields
and using a memory offset based scheme for.

Discovered and tested by temporarily putting the following debug
instrumentation into board_init():
    struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
    printf("&amp;anadig-&gt;pll3_ctrl=0x%p\n", &amp;anadig-&gt;pll3_ctrl);
    printf("&amp;anadig-&gt;pll5_ctrl=0x%p\n", &amp;anadig-&gt;pll5_ctrl);

Signed-off-by: Marcel Ziswiler &lt;marcel@ziswiler.com&gt;
[stefan@agner.ch: regrouped patch]
Signed-off-by: Stefan Agner &lt;stefan@agner.ch&gt;
</content>
</entry>
<entry>
<title>armv8/cache: Change cache invalidate and flush function</title>
<updated>2014-04-07T15:43:41Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2014-02-26T21:26:04Z</published>
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<id>urn:sha1:1e6ad55c058200010bb0649524a2c874e7049242</id>
<content type='text'>
When SoC first boots up, we should invalidate the cache but not flush it.
We can use the same function for invalid and flush mostly, with a wrapper.

Invalidating large cache can ben slow on emulator, so we postpone doing
so until I-cache is enabled, and before enabling D-cache.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
CC: David Feng &lt;fenghua@phytium.com.cn&gt;
</content>
</entry>
<entry>
<title>socfpga: Adding Clock Manager driver</title>
<updated>2014-04-07T08:41:50Z</updated>
<author>
<name>Chin Liang See</name>
<email>clsee@altera.com</email>
</author>
<published>2014-03-05T04:13:53Z</published>
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<id>urn:sha1:ddfeb0aaf49e30afff04e7a619913f09c2d4ce45</id>
<content type='text'>
Clock Manager driver will be called to reconfigure all the
clocks setting based on user input. The input are passed to
Preloader through handoff files

Signed-off-by: Chin Liang See &lt;clsee@altera.com&gt;
Cc: Albert Aribaud &lt;albert.u.boot@aribaud.net&gt;
Cc: Tom Rini &lt;trini@ti.com&gt;
Cc: Wolfgang Denk &lt;wd@denx.de&gt;
CC: Pavel Machek &lt;pavel@denx.de&gt;
Cc: Dinh Nguyen &lt;dinguyen@altera.com&gt;
Acked-by: Pavel Machek &lt;pavel@denx.de&gt;
</content>
</entry>
<entry>
<title>cpu: exynos4: add ace sha base address</title>
<updated>2014-03-28T19:06:31Z</updated>
<author>
<name>Przemyslaw Marczak</name>
<email>p.marczak@samsung.com</email>
</author>
<published>2014-03-25T09:58:20Z</published>
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<id>urn:sha1:680d8f03ea558f5d75f0506d8ca24db99508e4b2</id>
<content type='text'>
Signed-off-by: Przemyslaw Marczak &lt;p.marczak@samsung.com&gt;
Cc: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</content>
</entry>
<entry>
<title>spl: Fix guardian macros in spl.h</title>
<updated>2014-03-28T19:06:30Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2014-03-19T01:02:55Z</published>
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<id>urn:sha1:463bb19eebab4a5517c60dc9e74de0cc12c19e56</id>
<content type='text'>
Fix the macros guarding the spl.h header for various platforms. Due to
a typo and a propagation of it, the macros went out-of-sync with their
ifdef check, so fix this.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Tom Rini &lt;trini@ti.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'u-boot/master' into 'u-boot-arm/master'</title>
<updated>2014-03-25T09:53:15Z</updated>
<author>
<name>Albert ARIBAUD</name>
<email>albert.u.boot@aribaud.net</email>
</author>
<published>2014-03-25T09:25:14Z</published>
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<id>urn:sha1:ab6423cae0323e8db2c8fdd0a99138d93fde2137</id>
<content type='text'>
Trivial merge conflict, needed to manually remove
local_info as per commit 41364f0f.

Conflicts:
	board/samsung/common/board.c
</content>
</entry>
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