u-boot.git/arch/arm/include, branch v2015.10

Merge git://git.denx.de/u-boot-socfpga

2015-10-17T00:21:04Z

arm: socfpga: enable data/inst prefetch and shared override in the L2

2015-10-16T23:47:31Z

Update the L2 AUX CTRL settings for the SoCFPGA. Enabling D and I prefetch bits helps improve SDRAM performance on the platform. Also, we need to enable bit 22 of the L2. By not having bit 22 set in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. Signed-off-by: Dinh Nguyen

arm: mmu: Add missing volatile for reading SCTLR register

2015-10-16T05:55:51Z

Add 'volatile' qualifier to the asm statement in get_cr() so that the statement is not optimized out by the compiler. (http://comments.gmane.org/gmane.linux.linaro.toolchain/5163) Without the 'volatile', get_cr() returns a wrong value which prevents enabling the MMU and later causes a PCIE VA access failure. Signed-off-by: Alison Wang

Merge branch 'master' of git://git.denx.de/u-boot-arm

2015-10-15T21:45:39Z

pci: pcie_imx: Fix hang on mx6qp

2015-10-15T13:05:13Z

PCI driver currently hangs on mx6qp. Toggle the reset bit with the appropriate timings to fix the issue. Based on the FSL kernel driver implementation. Signed-off-by: Fabio Estevam Acked-by: Stefano Babic

armv8/mmu: Set bits marked RES1 in TCR

2015-10-15T12:46:43Z

For EL3 and EL2, the documentation says that bits 31 and 23 are reserved but should be written as 1. For EL1, only bit 23 is not reserved, so only write bit 31 as 1. Cc: Albert Aribaud Cc: Marc Zyngier Signed-off-by: Thierry Reding

armv8/mmu: Clean up TCR programming

2015-10-15T12:41:20Z

Use the inner shareable attribute for memory, which makes more sense considering that this code is called when caches are being enabled. Cc: Albert Aribaud Cc: Marc Zyngier Signed-off-by: Thierry Reding

lpc32xx: remove surplus clock cycle in PL175 WAIT_OEN config

2015-10-11T21:12:13Z

According to ARM PrimeCell PL175 documentation WAIT_OEN config value is defined without any additional clocks added to the value set by a client, the change fixes the wrong interface to WAIT_OEN config. The change also touches a single user of LPC32xx EMC and corrects configured "output enable delay" value on its side according to the changed interface. No functional change intended. Signed-off-by: Vladimir Zapolskiy

Merge branch 'master' of git://www.denx.de/git/u-boot-imx

2015-10-02T13:38:44Z

vf610: refactor DDRMC code

2015-10-02T08:42:31Z

The VF610 DDRMC driver code contains settings which are board-specific. Move these out to boards so that new boards can define their own without having to modify the driver. Signed-off-by: Albert ARIBAUD (3ADEV)