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<title>u-boot.git/arch/arm/include, branch v2016.05-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/include?h=v2016.05-rc2</id>
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<updated>2016-04-18T21:11:44Z</updated>
<entry>
<title>ARM: AM43xx: Fix BOOT_DEVICE_USB ID</title>
<updated>2016-04-18T21:11:44Z</updated>
<author>
<name>Lokesh Vutla</name>
<email>lokeshvutla@ti.com</email>
</author>
<published>2016-04-13T04:27:04Z</published>
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<id>urn:sha1:bd716dd03d8f22fe91924e43f4d1f69733570e60</id>
<content type='text'>
commit 62c5674ea136a ("omap: SPL boot devices cleanup and completion")
cleans up the boot device ids for amx3xx soc. But mistakenly updates wrong
device IDs for AM43xx USB. Fixing the same here.

Signed-off-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://www.denx.de/git/u-boot-imx</title>
<updated>2016-04-13T11:19:50Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-04-13T11:19:50Z</published>
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<id>urn:sha1:814013253fd4cf932d0fb32f7043f09a2a748d9a</id>
<content type='text'>
</content>
</entry>
<entry>
<title>am33xx changed BOOT_DEVICE_SPI to correct value</title>
<updated>2016-04-12T00:48:24Z</updated>
<author>
<name>Vogt, Christof</name>
<email>Christof.Vogt@comsoft.de</email>
</author>
<published>2016-04-05T08:56:57Z</published>
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<id>urn:sha1:7f961c90d76a485e16b2c52f6f66e58c909a5545</id>
<content type='text'>
Changed BOOT_DEVICE Code for SPI on AM33xx.
According AM335x reference manual page 4960
(SPRUH73L-October 2011-Revised February 2015)
Reviewed-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
</content>
</entry>
<entry>
<title>arm: add missing writes[bwql], reads[bwql].</title>
<updated>2016-04-10T15:18:41Z</updated>
<author>
<name>Purna Chandra Mandal</name>
<email>purna.mandal@microchip.com</email>
</author>
<published>2016-03-21T07:35:40Z</published>
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<id>urn:sha1:f968467785b8dc04e86b1249b5109cc410ae30c5</id>
<content type='text'>
ARM defines __raw_writes[bwql], __raw_reads[bwql] in arch io.h
but not the writes[bwql], reads[bwql] needed by some drivers.

Signed-off-by: Purna Chandra Mandal &lt;purna.mandal@microchip.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq</title>
<updated>2016-04-06T18:17:22Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-04-06T18:17:22Z</published>
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<id>urn:sha1:43d3fb5c0609a76409e7859a2a5800670c7b5bd2</id>
<content type='text'>
</content>
</entry>
<entry>
<title>armv8: LS2080A: Consolidate LS2080A and LS2085A</title>
<updated>2016-04-06T17:26:46Z</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2016-04-04T18:41:26Z</published>
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<id>urn:sha1:3c1d218a1d3048fb576677c47eab43049d0b7778</id>
<content type='text'>
LS2080A is the primary SoC, and LS2085A is a personality with AIOP
and DPAA DDR. The RDB and QDS boards support both personality. By
detecting the SVR at runtime, a single image per board can support
both SoCs. It gives users flexibility to swtich SoC without the need
to reprogram the board.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
CC: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
Reviewed-by: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
</content>
</entry>
<entry>
<title>arm: ls102xa: Fix order of CSU indexes in ns_access.h</title>
<updated>2016-04-06T17:26:21Z</updated>
<author>
<name>Vincent Siles</name>
<email>vincent.siles@provenrun.com</email>
</author>
<published>2016-03-29T07:41:16Z</published>
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<id>urn:sha1:96077896ee01d890d2758ce39aaf81af5f60dc59</id>
<content type='text'>
This patch aims to fix the order of CSU slave index for the LS1021a
board.

Signed-off-by: Vincent Siles &lt;vincent.siles@provenrun.com&gt;
Reviewed-by: Alison Wang &lt;alison.wang@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>armv8: LSCH2 early and final mmu needs matching NS attribute</title>
<updated>2016-04-06T15:35:09Z</updated>
<author>
<name>Ed Swarthout</name>
<email>Ed.Swarthout@nxp.com</email>
</author>
<published>2016-03-28T21:16:01Z</published>
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<id>urn:sha1:70e21b06425ad6e1e90931333a704a600941cfff</id>
<content type='text'>
When switching between the early and final mmu tables, the stack will
get corrupted if the Non-Secure attribute is different.  For ls1043a,
this issue is currently masked because flush_dcache_all is called
before the switch when CONFIG_SYS_DPAA_FMAN is defined.

Signed-off-by: Ed Swarthout &lt;Ed.Swarthout@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>spi: kirkwood_spi: Add support for multiple chip-selects on MVEBU</title>
<updated>2016-04-06T13:38:56Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2016-02-11T10:37:38Z</published>
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<id>urn:sha1:9fc56631a4f784ecaf860ae822d48580cd4317ed</id>
<content type='text'>
Currently only chip-select 0 is supported by the kirkwood SPI driver.
The Armada XP / 38x SoCs also use this driver and support multiple chip
selects. This patch adds support for multiple CS on MVEBU.

The register definitions are restructured a bit with this patch. Grouping
them to the corresponding registers.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Luka Perkov &lt;luka.perkov@sartura.hr&gt;
Reviewed-by: Jagan Teki &lt;jteki@openedev.com&gt;
</content>
</entry>
<entry>
<title>sunxi: Add support for Allwinner A64 SoCs</title>
<updated>2016-04-01T07:52:28Z</updated>
<author>
<name>Siarhei Siamashka</name>
<email>siarhei.siamashka@gmail.com</email>
</author>
<published>2016-03-29T15:29:10Z</published>
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<id>urn:sha1:d96ebc468d0dff6eb6f069bba03b3f0e33aa22de</id>
<content type='text'>
The Allwinner A64 SoC is used in the Pine64. This patch adds
all bits necessary to compile U-Boot for it running in AArch64
mode.

Unfortunately SPL is not ready yet due to legal problems, so
we need to boot using the binary boot0 for now.

Signed-off-by: Siarhei Siamashka &lt;siarhei.siamashka@gmail.com&gt;
[agraf: remove SPL code, move to AArch64]
Signed-off-by: Alexander Graf &lt;agraf@suse.de&gt;
Acked-by: Hans de Goede &lt;hdegoede@redhat.com&gt;
Signed-off-by: Hans de Goede &lt;hdegoede@redhat.com&gt;
</content>
</entry>
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