<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/arch/arm/include, branch v2016.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>Merge branch 'master' of git://www.denx.de/git/u-boot-imx</title>
<updated>2016-09-09T13:45:32+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-09-09T13:45:32+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=16f416661ec5ffa46b3f879a0b83907bbec13714'/>
<id>16f416661ec5ffa46b3f879a0b83907bbec13714</id>
<content type='text'>
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>TI: Rework SRAM definitions and maximums</title>
<updated>2016-09-06T17:41:42+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-08-26T17:30:43+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=fa2f81b06f666710c756d25297d7a9ca48c65935'/>
<id>fa2f81b06f666710c756d25297d7a9ca48c65935</id>
<content type='text'>
On all TI platforms the ROM defines a "downloaded image" area at or near
the start of SRAM which is followed by a reserved area.  As it is at
best bad form and at worst possibly harmful in corner cases to write in
this reserved area, we stop doing that by adding in the define
NON_SECURE_SRAM_IMG_END to say where the end of the downloaded image
area is and make SRAM_SCRATCH_SPACE_ADDR be one kilobyte before this.
At current we define the end of scratch space at 0x228 bytes past the
start of scratch space this this gives us a lot of room to grow.  As
these scratch uses are non-optional today, all targets are modified to
respect this boundary.

Tested on OMAP4 Pandaboard, OMAP3 Beagle xM

Cc: Albert Aribaud &lt;albert.u.boot@aribaud.net&gt;
Cc: Nagendra T S &lt;nagendra@mistralsolutions.com&gt;
Cc: Vaibhav Hiremath &lt;hvaibhav@ti.com&gt;
Cc: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
Cc: Felipe Balbi &lt;balbi@ti.com&gt;
Cc: Igor Grinberg &lt;grinberg@compulab.co.il&gt;
Cc: Nikita Kiryanov &lt;nikita@compulab.co.il&gt;
Cc: Paul Kocialkowski &lt;contact@paulk.fr&gt;
Cc: Enric Balletbo i Serra &lt;eballetbo@gmail.com&gt;
Cc: Adam Ford &lt;aford173@gmail.com&gt;
Cc: Steve Sakoman &lt;sakoman@gmail.com&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Cc: Thomas Weber &lt;weber@corscience.de&gt;
Cc: Hannes Schmelzer &lt;oe5hpm@oevsv.at&gt;
Cc: Thomas Chou &lt;thomas@wytron.com.tw&gt;
Cc: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Cc: Sam Protsenko &lt;semen.protsenko@linaro.org&gt;
Cc: Heiko Schocher &lt;hs@denx.de&gt;
Cc: Samuel Egli &lt;samuel.egli@siemens.com&gt;
Cc: Michal Simek &lt;michal.simek@xilinx.com&gt;
Cc: Wolfgang Denk &lt;wd@denx.de&gt;
Cc: Mateusz Kulikowski &lt;mateusz.kulikowski@gmail.com&gt;
Cc: Ben Whitten &lt;ben.whitten@gmail.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Cc: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Cc: Sekhar Nori &lt;nsekhar@ti.com&gt;
Cc: Mugunthan V N &lt;mugunthanvnm@ti.com&gt;
Cc: "B, Ravi" &lt;ravibabu@ti.com&gt;
Cc: "Matwey V. Kornilov" &lt;matwey.kornilov@gmail.com&gt;
Cc: Ladislav Michl &lt;ladis@linux-mips.org&gt;
Cc: Ash Charles &lt;ashcharles@gmail.com&gt;
Cc: "Kipisz, Steven" &lt;s-kipisz2@ti.com&gt;
Cc: Daniel Allred &lt;d-allred@ti.com&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
Tested-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
Acked-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
Tested-by: Ladislav Michl &lt;ladis@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
On all TI platforms the ROM defines a "downloaded image" area at or near
the start of SRAM which is followed by a reserved area.  As it is at
best bad form and at worst possibly harmful in corner cases to write in
this reserved area, we stop doing that by adding in the define
NON_SECURE_SRAM_IMG_END to say where the end of the downloaded image
area is and make SRAM_SCRATCH_SPACE_ADDR be one kilobyte before this.
At current we define the end of scratch space at 0x228 bytes past the
start of scratch space this this gives us a lot of room to grow.  As
these scratch uses are non-optional today, all targets are modified to
respect this boundary.

Tested on OMAP4 Pandaboard, OMAP3 Beagle xM

Cc: Albert Aribaud &lt;albert.u.boot@aribaud.net&gt;
Cc: Nagendra T S &lt;nagendra@mistralsolutions.com&gt;
Cc: Vaibhav Hiremath &lt;hvaibhav@ti.com&gt;
Cc: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
Cc: Felipe Balbi &lt;balbi@ti.com&gt;
Cc: Igor Grinberg &lt;grinberg@compulab.co.il&gt;
Cc: Nikita Kiryanov &lt;nikita@compulab.co.il&gt;
Cc: Paul Kocialkowski &lt;contact@paulk.fr&gt;
Cc: Enric Balletbo i Serra &lt;eballetbo@gmail.com&gt;
Cc: Adam Ford &lt;aford173@gmail.com&gt;
Cc: Steve Sakoman &lt;sakoman@gmail.com&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Cc: Thomas Weber &lt;weber@corscience.de&gt;
Cc: Hannes Schmelzer &lt;oe5hpm@oevsv.at&gt;
Cc: Thomas Chou &lt;thomas@wytron.com.tw&gt;
Cc: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Cc: Sam Protsenko &lt;semen.protsenko@linaro.org&gt;
Cc: Heiko Schocher &lt;hs@denx.de&gt;
Cc: Samuel Egli &lt;samuel.egli@siemens.com&gt;
Cc: Michal Simek &lt;michal.simek@xilinx.com&gt;
Cc: Wolfgang Denk &lt;wd@denx.de&gt;
Cc: Mateusz Kulikowski &lt;mateusz.kulikowski@gmail.com&gt;
Cc: Ben Whitten &lt;ben.whitten@gmail.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Cc: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Cc: Sekhar Nori &lt;nsekhar@ti.com&gt;
Cc: Mugunthan V N &lt;mugunthanvnm@ti.com&gt;
Cc: "B, Ravi" &lt;ravibabu@ti.com&gt;
Cc: "Matwey V. Kornilov" &lt;matwey.kornilov@gmail.com&gt;
Cc: Ladislav Michl &lt;ladis@linux-mips.org&gt;
Cc: Ash Charles &lt;ashcharles@gmail.com&gt;
Cc: "Kipisz, Steven" &lt;s-kipisz2@ti.com&gt;
Cc: Daniel Allred &lt;d-allred@ti.com&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
Tested-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
Acked-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
Tested-by: Ladislav Michl &lt;ladis@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>meson: odroid-c2: enable Ethernet support through the device tree</title>
<updated>2016-09-06T17:18:19+00:00</updated>
<author>
<name>Beniamino Galvani</name>
<email>b.galvani@gmail.com</email>
</author>
<published>2016-08-16T09:49:50+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=cfe255611ce183187a3de5ef6fed246bdea7b044'/>
<id>cfe255611ce183187a3de5ef6fed246bdea7b044</id>
<content type='text'>
Remove the device definition from board file, update the driver with
the new compatible property and update config with necessary options.

Signed-off-by: Beniamino Galvani &lt;b.galvani@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Remove the device definition from board file, update the driver with
the new compatible property and update config with necessary options.

Signed-off-by: Beniamino Galvani &lt;b.galvani@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mx6: ddr: Allow changing REFSEL and REFR fields</title>
<updated>2016-09-06T16:22:48+00:00</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@nxp.com</email>
</author>
<published>2016-08-29T23:37:15+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=edf0093732225c2fd0791c3864e9a3eef1f92f19'/>
<id>edf0093732225c2fd0791c3864e9a3eef1f92f19</id>
<content type='text'>
Currently MX6 SPL DDR initialization hardcodes the REF_SEL and
REFR fields of the MDREF register as 1 and 7, respectively for
DDR3 and 0 and 3 for LPDDR2.

Looking at the MDREF initialization done via DCD we see that
boards do need to initialize these fields differently:

$ git grep 0x021b0020 board/
board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4      0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800
board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800

So introduce a mechanism for users to be able to configure
REFSEL and REFR fields as needed.

Keep all the mx6 SPL users in their current REF_SEL and REFR values,
so no functional changes for the existing users.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Reviewed-by: Eric Nelson &lt;eric@nelint.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Currently MX6 SPL DDR initialization hardcodes the REF_SEL and
REFR fields of the MDREF register as 1 and 7, respectively for
DDR3 and 0 and 3 for LPDDR2.

Looking at the MDREF initialization done via DCD we see that
boards do need to initialize these fields differently:

$ git grep 0x021b0020 board/
board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4      0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800
board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800

So introduce a mechanism for users to be able to configure
REFSEL and REFR fields as needed.

Keep all the mx6 SPL users in their current REF_SEL and REFR values,
so no functional changes for the existing users.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Reviewed-by: Eric Nelson &lt;eric@nelint.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'master' of http://git.denx.de/u-boot-sunxi</title>
<updated>2016-08-26T21:05:01+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-08-26T18:58:52+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c6b968da78ce3fa7224c0ddf15fe170c7c05b27e'/>
<id>c6b968da78ce3fa7224c0ddf15fe170c7c05b27e</id>
<content type='text'>
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: Move SYS_CACHELINE_SIZE over to Kconfig</title>
<updated>2016-08-26T21:04:46+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-08-22T12:22:17+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=067716bac59716b07f1ee70d9bf6e5528289bb45'/>
<id>067716bac59716b07f1ee70d9bf6e5528289bb45</id>
<content type='text'>
This series moves the CONFIG_SYS_CACHELINE_SIZE.  First, in nearly all
cases we are mirroring the values used by the Linux Kernel here.  Also,
so long as (and in this case, it is true) we implement flushes in hunks
that are no larger than the smallest implementation (and given that we
mirror the Linux Kernel, again we are fine) it is OK to align higher.
The biggest changes here are that we always use 64 bytes for CPU_V7 even
if for example the underlying core is only 32 bytes (this mirrors
Linux).  Second, we say ARM64 uses 64 bytes not 128 (as found in the
Linux Kernel) as we do not need multi-platform support (to this degree)
and only the Cavium ThunderX 88xx series has a use for such large
alignment.

Cc: Albert Aribaud &lt;albert.u.boot@aribaud.net&gt;
Cc: Marek Vasut &lt;marex@denx.de&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Cc: Prafulla Wadaskar &lt;prafulla@marvell.com&gt;
Cc: Luka Perkov &lt;luka.perkov@sartura.hr&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Cc: Nagendra T S &lt;nagendra@mistralsolutions.com&gt;
Cc: Vaibhav Hiremath &lt;hvaibhav@ti.com&gt;
Acked-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
Cc: Steve Rae &lt;steve.rae@raedomain.com&gt;
Cc: Igor Grinberg &lt;grinberg@compulab.co.il&gt;
Cc: Nikita Kiryanov &lt;nikita@compulab.co.il&gt;
Cc: Stefan Agner &lt;stefan.agner@toradex.com&gt;
Acked-by: Heiko Schocher &lt;hs@denx.de&gt;
Cc: Mateusz Kulikowski &lt;mateusz.kulikowski@gmail.com&gt;
Cc: Peter Griffin &lt;peter.griffin@linaro.org&gt;
Acked-by: Paul Kocialkowski &lt;contact@paulk.fr&gt;
Cc: Anatolij Gustschin &lt;agust@denx.de&gt;
Acked-by: "Pali Rohár" &lt;pali.rohar@gmail.com&gt;
Cc: Adam Ford &lt;aford173@gmail.com&gt;
Cc: Steve Sakoman &lt;sakoman@gmail.com&gt;
Cc: Grazvydas Ignotas &lt;notasas@gmail.com&gt;
Cc: Nishanth Menon &lt;nm@ti.com&gt;
Cc: Stephen Warren &lt;swarren@wwwdotorg.org&gt;
Cc: Robert Baldyga &lt;r.baldyga@samsung.com&gt;
Cc: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
Cc: Thomas Weber &lt;weber@corscience.de&gt;
Cc: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Cc: David Feng &lt;fenghua@phytium.com.cn&gt;
Cc: Alison Wang &lt;b18965@freescale.com&gt;
Cc: Michal Simek &lt;michal.simek@xilinx.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: York Sun &lt;york.sun@nxp.com&gt;
Cc: Shengzhou Liu &lt;Shengzhou.Liu@nxp.com&gt;
Cc: Mingkai Hu &lt;mingkai.hu@nxp.com&gt;
Cc: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
Cc: Aneesh Bansal &lt;aneesh.bansal@freescale.com&gt;
Cc: Saksham Jain &lt;saksham.jain@nxp.com&gt;
Cc: Qianyu Gong &lt;qianyu.gong@nxp.com&gt;
Cc: Wang Dongsheng &lt;dongsheng.wang@nxp.com&gt;
Cc: Alex Porosanu &lt;alexandru.porosanu@freescale.com&gt;
Cc: Hongbo Zhang &lt;hongbo.zhang@nxp.com&gt;
Cc: tang yuantian &lt;Yuantian.Tang@freescale.com&gt;
Cc: Rajesh Bhagat &lt;rajesh.bhagat@nxp.com&gt;
Cc: Josh Wu &lt;josh.wu@atmel.com&gt;
Cc: Bo Shen &lt;voice.shen@atmel.com&gt;
Cc: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
Cc: Hannes Schmelzer &lt;oe5hpm@oevsv.at&gt;
Cc: Thomas Chou &lt;thomas@wytron.com.tw&gt;
Cc: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Cc: Sam Protsenko &lt;semen.protsenko@linaro.org&gt;
Cc: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Cc: Christophe Ricard &lt;christophe-h.ricard@st.com&gt;
Cc: Anand Moon &lt;linux.amoon@gmail.com&gt;
Cc: Beniamino Galvani &lt;b.galvani@gmail.com&gt;
Cc: Carlo Caione &lt;carlo@endlessm.com&gt;
Cc: huang lin &lt;hl@rock-chips.com&gt;
Cc: Sjoerd Simons &lt;sjoerd.simons@collabora.co.uk&gt;
Cc: Xu Ziyuan &lt;xzy.xu@rock-chips.com&gt;
Cc: "jk.kernel@gmail.com" &lt;jk.kernel@gmail.com&gt;
Cc: "Ariel D'Alessandro" &lt;ariel@vanguardiasur.com.ar&gt;
Cc: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Cc: Samuel Egli &lt;samuel.egli@siemens.com&gt;
Cc: Chin Liang See &lt;clsee@altera.com&gt;
Cc: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
Cc: Hans de Goede &lt;hdegoede@redhat.com&gt;
Cc: Ian Campbell &lt;ijc@hellion.org.uk&gt;
Cc: Siarhei Siamashka &lt;siarhei.siamashka@gmail.com&gt;
Cc: Boris Brezillon &lt;boris.brezillon@free-electrons.com&gt;
Cc: Andre Przywara &lt;andre.przywara@arm.com&gt;
Cc: Bernhard Nortmann &lt;bernhard.nortmann@web.de&gt;
Cc: Wolfgang Denk &lt;wd@denx.de&gt;
Cc: Ben Whitten &lt;ben.whitten@gmail.com&gt;
Cc: Tom Warren &lt;twarren@nvidia.com&gt;
Cc: Alexander Graf &lt;agraf@suse.de&gt;
Cc: Sekhar Nori &lt;nsekhar@ti.com&gt;
Cc: Vitaly Andrianov &lt;vitalya@ti.com&gt;
Cc: "Andrew F. Davis" &lt;afd@ti.com&gt;
Cc: Murali Karicheri &lt;m-karicheri2@ti.com&gt;
Cc: Carlos Hernandez &lt;ceh@ti.com&gt;
Cc: Ladislav Michl &lt;ladis@linux-mips.org&gt;
Cc: Ash Charles &lt;ashcharles@gmail.com&gt;
Cc: Mugunthan V N &lt;mugunthanvnm@ti.com&gt;
Cc: Daniel Allred &lt;d-allred@ti.com&gt;
Cc: Gong Qianyu &lt;Qianyu.Gong@freescale.com&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
Acked-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Acked-by: Chin Liang See &lt;clsee@altera.com&gt;
Tested-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Acked-by: Paul Kocialkowski &lt;contact@paulk.fr&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This series moves the CONFIG_SYS_CACHELINE_SIZE.  First, in nearly all
cases we are mirroring the values used by the Linux Kernel here.  Also,
so long as (and in this case, it is true) we implement flushes in hunks
that are no larger than the smallest implementation (and given that we
mirror the Linux Kernel, again we are fine) it is OK to align higher.
The biggest changes here are that we always use 64 bytes for CPU_V7 even
if for example the underlying core is only 32 bytes (this mirrors
Linux).  Second, we say ARM64 uses 64 bytes not 128 (as found in the
Linux Kernel) as we do not need multi-platform support (to this degree)
and only the Cavium ThunderX 88xx series has a use for such large
alignment.

Cc: Albert Aribaud &lt;albert.u.boot@aribaud.net&gt;
Cc: Marek Vasut &lt;marex@denx.de&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Cc: Prafulla Wadaskar &lt;prafulla@marvell.com&gt;
Cc: Luka Perkov &lt;luka.perkov@sartura.hr&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Cc: Nagendra T S &lt;nagendra@mistralsolutions.com&gt;
Cc: Vaibhav Hiremath &lt;hvaibhav@ti.com&gt;
Acked-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
Cc: Steve Rae &lt;steve.rae@raedomain.com&gt;
Cc: Igor Grinberg &lt;grinberg@compulab.co.il&gt;
Cc: Nikita Kiryanov &lt;nikita@compulab.co.il&gt;
Cc: Stefan Agner &lt;stefan.agner@toradex.com&gt;
Acked-by: Heiko Schocher &lt;hs@denx.de&gt;
Cc: Mateusz Kulikowski &lt;mateusz.kulikowski@gmail.com&gt;
Cc: Peter Griffin &lt;peter.griffin@linaro.org&gt;
Acked-by: Paul Kocialkowski &lt;contact@paulk.fr&gt;
Cc: Anatolij Gustschin &lt;agust@denx.de&gt;
Acked-by: "Pali Rohár" &lt;pali.rohar@gmail.com&gt;
Cc: Adam Ford &lt;aford173@gmail.com&gt;
Cc: Steve Sakoman &lt;sakoman@gmail.com&gt;
Cc: Grazvydas Ignotas &lt;notasas@gmail.com&gt;
Cc: Nishanth Menon &lt;nm@ti.com&gt;
Cc: Stephen Warren &lt;swarren@wwwdotorg.org&gt;
Cc: Robert Baldyga &lt;r.baldyga@samsung.com&gt;
Cc: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
Cc: Thomas Weber &lt;weber@corscience.de&gt;
Cc: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Cc: David Feng &lt;fenghua@phytium.com.cn&gt;
Cc: Alison Wang &lt;b18965@freescale.com&gt;
Cc: Michal Simek &lt;michal.simek@xilinx.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: York Sun &lt;york.sun@nxp.com&gt;
Cc: Shengzhou Liu &lt;Shengzhou.Liu@nxp.com&gt;
Cc: Mingkai Hu &lt;mingkai.hu@nxp.com&gt;
Cc: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
Cc: Aneesh Bansal &lt;aneesh.bansal@freescale.com&gt;
Cc: Saksham Jain &lt;saksham.jain@nxp.com&gt;
Cc: Qianyu Gong &lt;qianyu.gong@nxp.com&gt;
Cc: Wang Dongsheng &lt;dongsheng.wang@nxp.com&gt;
Cc: Alex Porosanu &lt;alexandru.porosanu@freescale.com&gt;
Cc: Hongbo Zhang &lt;hongbo.zhang@nxp.com&gt;
Cc: tang yuantian &lt;Yuantian.Tang@freescale.com&gt;
Cc: Rajesh Bhagat &lt;rajesh.bhagat@nxp.com&gt;
Cc: Josh Wu &lt;josh.wu@atmel.com&gt;
Cc: Bo Shen &lt;voice.shen@atmel.com&gt;
Cc: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
Cc: Hannes Schmelzer &lt;oe5hpm@oevsv.at&gt;
Cc: Thomas Chou &lt;thomas@wytron.com.tw&gt;
Cc: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Cc: Sam Protsenko &lt;semen.protsenko@linaro.org&gt;
Cc: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Cc: Christophe Ricard &lt;christophe-h.ricard@st.com&gt;
Cc: Anand Moon &lt;linux.amoon@gmail.com&gt;
Cc: Beniamino Galvani &lt;b.galvani@gmail.com&gt;
Cc: Carlo Caione &lt;carlo@endlessm.com&gt;
Cc: huang lin &lt;hl@rock-chips.com&gt;
Cc: Sjoerd Simons &lt;sjoerd.simons@collabora.co.uk&gt;
Cc: Xu Ziyuan &lt;xzy.xu@rock-chips.com&gt;
Cc: "jk.kernel@gmail.com" &lt;jk.kernel@gmail.com&gt;
Cc: "Ariel D'Alessandro" &lt;ariel@vanguardiasur.com.ar&gt;
Cc: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Cc: Samuel Egli &lt;samuel.egli@siemens.com&gt;
Cc: Chin Liang See &lt;clsee@altera.com&gt;
Cc: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
Cc: Hans de Goede &lt;hdegoede@redhat.com&gt;
Cc: Ian Campbell &lt;ijc@hellion.org.uk&gt;
Cc: Siarhei Siamashka &lt;siarhei.siamashka@gmail.com&gt;
Cc: Boris Brezillon &lt;boris.brezillon@free-electrons.com&gt;
Cc: Andre Przywara &lt;andre.przywara@arm.com&gt;
Cc: Bernhard Nortmann &lt;bernhard.nortmann@web.de&gt;
Cc: Wolfgang Denk &lt;wd@denx.de&gt;
Cc: Ben Whitten &lt;ben.whitten@gmail.com&gt;
Cc: Tom Warren &lt;twarren@nvidia.com&gt;
Cc: Alexander Graf &lt;agraf@suse.de&gt;
Cc: Sekhar Nori &lt;nsekhar@ti.com&gt;
Cc: Vitaly Andrianov &lt;vitalya@ti.com&gt;
Cc: "Andrew F. Davis" &lt;afd@ti.com&gt;
Cc: Murali Karicheri &lt;m-karicheri2@ti.com&gt;
Cc: Carlos Hernandez &lt;ceh@ti.com&gt;
Cc: Ladislav Michl &lt;ladis@linux-mips.org&gt;
Cc: Ash Charles &lt;ashcharles@gmail.com&gt;
Cc: Mugunthan V N &lt;mugunthanvnm@ti.com&gt;
Cc: Daniel Allred &lt;d-allred@ti.com&gt;
Cc: Gong Qianyu &lt;Qianyu.Gong@freescale.com&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
Acked-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Acked-by: Chin Liang See &lt;clsee@altera.com&gt;
Tested-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Acked-by: Paul Kocialkowski &lt;contact@paulk.fr&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sunxi: Tune H3 DRAM PLL to improve lock time</title>
<updated>2016-08-26T14:58:37+00:00</updated>
<author>
<name>Jens Kuske</name>
<email>jenskuske@gmail.com</email>
</author>
<published>2016-08-19T11:40:46+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d5ac6eef91965b519d8f15f17febfa0ea2ee0adc'/>
<id>d5ac6eef91965b519d8f15f17febfa0ea2ee0adc</id>
<content type='text'>
The H3 PLL5 used for DRAM barely manages to lock to the required
frequency before DRAM controller starts, sometimes leading to wrong
delay-line calibration results.
This patch changes the PLL tuning parameters to the same values as
boot0 used, which speeds up the locking and fixes the problem.

Signed-off-by: Jens Kuske &lt;jenskuske@gmail.com&gt;
Reviewed-by: Hans de Goede &lt;hdegoede@redhat.com&gt;
Signed-off-by: Hans de Goede &lt;hdegoede@redhat.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The H3 PLL5 used for DRAM barely manages to lock to the required
frequency before DRAM controller starts, sometimes leading to wrong
delay-line calibration results.
This patch changes the PLL tuning parameters to the same values as
boot0 used, which speeds up the locking and fixes the problem.

Signed-off-by: Jens Kuske &lt;jenskuske@gmail.com&gt;
Reviewed-by: Hans de Goede &lt;hdegoede@redhat.com&gt;
Signed-off-by: Hans de Goede &lt;hdegoede@redhat.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sunxi: display: Use PWM to drive backlight where applicable</title>
<updated>2016-08-26T14:58:37+00:00</updated>
<author>
<name>Hans de Goede</name>
<email>hdegoede@redhat.com</email>
</author>
<published>2016-08-19T13:25:41+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=421c98d7d2ebf929debf907e75ec04419cf07dbe'/>
<id>421c98d7d2ebf929debf907e75ec04419cf07dbe</id>
<content type='text'>
When the backlight's pwm input is connected to a pwm output of the SoC,
actually use pwm to drive the backlight.

The mean reason for doing this is to fix the backlight turning off
for aprox. 1 second while the kernel is booting. This is caused by
the kernel actually using pwm to drive the backlight, so that it
can dim the backlight. First the pwm driver loads and switches the
pinmux for the pin driving the backlight's pwm input to the pwm
controller. Then about 1s later the actual backlight driver loads
and tells the pwm driver to actually update the pwm settings, which
have a power-on-reset value of "off".

An additional advantage is that this allows us to initatiate the
backlight at 80%, which is the kernel default, avoiding a brightness
change while the kernel loads.

Signed-off-by: Hans de Goede &lt;hdegoede@redhat.com&gt;
Reviewed by: Peter Korsgaard &lt;peter@korsgaard.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
When the backlight's pwm input is connected to a pwm output of the SoC,
actually use pwm to drive the backlight.

The mean reason for doing this is to fix the backlight turning off
for aprox. 1 second while the kernel is booting. This is caused by
the kernel actually using pwm to drive the backlight, so that it
can dim the backlight. First the pwm driver loads and switches the
pinmux for the pin driving the backlight's pwm input to the pwm
controller. Then about 1s later the actual backlight driver loads
and tells the pwm driver to actually update the pwm settings, which
have a power-on-reset value of "off".

An additional advantage is that this allows us to initatiate the
backlight at 80%, which is the kernel default, avoiding a brightness
change while the kernel loads.

Signed-off-by: Hans de Goede &lt;hdegoede@redhat.com&gt;
Reviewed by: Peter Korsgaard &lt;peter@korsgaard.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'rmobile' of git://git.denx.de/u-boot-sh</title>
<updated>2016-08-20T20:40:34+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-08-20T15:35:28+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c98b171e1098f94b2ff7720c45a25a602882f876'/>
<id>c98b171e1098f94b2ff7720c45a25a602882f876</id>
<content type='text'>
[trini: Drop CMD_BOOTI as it's now on by default on ARM64]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
[trini: Drop CMD_BOOTI as it's now on by default on ARM64]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: rmobile: Move SoC headers to mach-rmobile/include/mach</title>
<updated>2016-08-17T01:25:34+00:00</updated>
<author>
<name>Nobuhiro Iwamatsu</name>
<email>iwamatsu@nigauri.org</email>
</author>
<published>2015-10-09T20:42:01+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7a7d246d97bc66e01bf030b0503b14f78f08629d'/>
<id>7a7d246d97bc66e01bf030b0503b14f78f08629d</id>
<content type='text'>
Move form arch/arm/include/asm/arch-rmobile/ to arch/arm/mach-rmobile/include/mach/.

Signed-off-by: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Move form arch/arm/include/asm/arch-rmobile/ to arch/arm/mach-rmobile/include/mach/.

Signed-off-by: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
