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<title>u-boot.git/arch/arm/include, branch v2017.03</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/include?h=v2017.03</id>
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<updated>2017-03-12T03:30:25Z</updated>
<entry>
<title>arm: OMAP2+: nandecc: propagate error to command return status</title>
<updated>2017-03-12T03:30:25Z</updated>
<author>
<name>Ladislav Michl</name>
<email>ladis@linux-mips.org</email>
</author>
<published>2017-03-06T12:54:30Z</published>
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<id>urn:sha1:50075153fe66d8f9a859191132e8f23f11ba57d4</id>
<content type='text'>
Currently nandecc returns zero even if underlaying
omap_nand_switch_ecc function fails. Fix that by
propagating error returned to command return value.

Signed-off-by: Ladislav Michl &lt;ladis@linux-mips.org&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>ARM: Migrate errata to Kconfig</title>
<updated>2017-03-10T00:52:50Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2017-03-07T12:13:42Z</published>
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<id>urn:sha1:8dda2e2f9e0976249f4a390e72f12533dbcb5ef4</id>
<content type='text'>
This moves all of the current ARM errata from various header files and in to
Kconfig.  This allows for a minor amount of cleanup as we had some instances
where both a general common header file was enabling errata as well as the
board config.  We now just select these once at the higher level in Kconfig

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>Freescale/NXP: Migrate CONFIG_FSL_CAAM to defconfigs</title>
<updated>2017-03-09T16:37:24Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2017-03-01T21:51:58Z</published>
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<id>urn:sha1:285226785ee178c0bbe8a67185c21e461cf4bc9f</id>
<content type='text'>
In some cases this is absolutely required, so select this for some secure
features.  This also requires migration of RSA_FREESCALE_EXP

Cc: Ruchika Gupta &lt;ruchika.gupta@nxp.com&gt;
Cc: Poonam Aggrwal &lt;poonam.aggrwal@freescale.com&gt;
Cc: Naveen Burmi &lt;NaveenBurmi@freescale.com&gt;
Cc: Po Liu &lt;po.liu@freescale.com&gt;
Cc: Shengzhou Liu &lt;Shengzhou.Liu@freescale.com&gt;
Cc: Priyanka Jain &lt;Priyanka.Jain@freescale.com&gt;
Cc: Sumit Garg &lt;sumit.garg@nxp.com&gt;
Cc: Shaohui Xie &lt;Shaohui.Xie@freescale.com&gt;
Cc: Chunhe Lan &lt;Chunhe.Lan@freescale.com&gt;
Cc: Feng Li &lt;feng.li_2@nxp.com&gt;
Cc: Alison Wang &lt;alison.wang@freescale.com&gt;
Cc: Mingkai Hu &lt;Mingkai.Hu@freescale.com&gt;
Cc: York Sun &lt;york.sun@nxp.com&gt;
Cc: Saksham Jain &lt;saksham.jain@nxp.freescale.com&gt;
Cc: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>armv5te: make 'ret lr' produce iinterworking 'bx lr'</title>
<updated>2017-03-02T02:28:31Z</updated>
<author>
<name>Albert ARIBAUD</name>
<email>albert.u.boot@aribaud.net</email>
</author>
<published>2017-02-27T19:19:07Z</published>
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<id>urn:sha1:6b4e9426834580810790ecfa924979d61c5c1987</id>
<content type='text'>
Current ARM assembler helper for the 'return to caller' pseudo-instruction
turns 'ret lr' into 'mov pc, lr' for ARMv5TE. This causes the core to remain
in its current ARM state even when the routine doing the 'ret' was called
from Thumb-1 state, triggering an undefined instruction exception.

This causes early run-time failures in all boards compiled using the Thumb-1
instruction set (for instance the Open-RD family).

ARMv5TE supports 'bx lr' which properly implements interworking and thus
correctly returns to Thumb-1 state from ARM state.

This change makes 'ret lr' turn into 'bx lr' for ARMv5TE.

Signed-off-by: Albert ARIBAUD &lt;albert.u.boot@aribaud.net&gt;
</content>
</entry>
<entry>
<title>ARM: DRA7xx: Fix memory allocation overflow</title>
<updated>2017-02-17T22:24:35Z</updated>
<author>
<name>Andrew F. Davis</name>
<email>afd@ti.com</email>
</author>
<published>2017-02-15T15:16:53Z</published>
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<id>urn:sha1:66c246cce7c66019a93ff7105157c3e2126dd277</id>
<content type='text'>
When using early malloc the allocated memory can overflow into the SRAM
scratch space, move NON_SECURE_SRAM_IMG_END down a bit to allow more
dynamic allocation at the expense of a slightly smaller maximum image
size.

Signed-off-by: Andrew F. Davis &lt;afd@ti.com&gt;
Reviewed-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
</content>
</entry>
<entry>
<title>Merge git://git.denx.de/u-boot-fsl-qoriq</title>
<updated>2017-02-04T01:33:42Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2017-02-04T01:33:42Z</published>
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<id>urn:sha1:c83a824e62277162ad35f52879b2316902c0eff5</id>
<content type='text'>
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;

Conflicts:
	configs/ls1046aqds_defconfig
	configs/ls1046aqds_nand_defconfig
	configs/ls1046aqds_qspi_defconfig
	configs/ls1046aqds_sdcard_ifc_defconfig
	configs/ls1046aqds_sdcard_qspi_defconfig
	configs/ls1046ardb_emmc_defconfig
	configs/ls1046ardb_qspi_defconfig
	configs/ls1046ardb_sdcard_defconfig
</content>
</entry>
<entry>
<title>board: freescale: ls1012a: Enable secure DDR on LS1012A platforms</title>
<updated>2017-02-03T22:30:28Z</updated>
<author>
<name>Prabhakar Kushwaha</name>
<email>prabhakar.kushwaha@nxp.com</email>
</author>
<published>2017-01-30T11:35:22Z</published>
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<id>urn:sha1:7d559604d03ea876038570df27d11c8dd5420d17</id>
<content type='text'>
PPA binary needs to be relocated on secure DDR, hence marking out
a portion of DDR as secure if CONFIG_SYS_MEM_RESERVE_SECURE flag
is set

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Signed-off-by: Abhimanyu Saini &lt;abhimanyu.saini@nxp.com&gt;
Signed-off-by: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://www.denx.de/git/u-boot-imx</title>
<updated>2017-02-01T21:34:25Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2017-02-01T21:34:25Z</published>
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<id>urn:sha1:43ade93bdb0c8bd57382be810a05b3793749ce85</id>
<content type='text'>
</content>
</entry>
<entry>
<title>ARM: SPI: stm32: add stm32f746 qspi driver</title>
<updated>2017-01-28T19:04:50Z</updated>
<author>
<name>Michael Kurz</name>
<email>michi.kurz@gmail.com</email>
</author>
<published>2017-01-22T15:04:30Z</published>
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<id>urn:sha1:d4363baada1505e126fc75c292f17903ab9c9e3a</id>
<content type='text'>
This patch adds support for the QSPI IP found in stm32f7 devices.

Signed-off-by: Michael Kurz &lt;michi.kurz@gmail.com&gt;
</content>
</entry>
<entry>
<title>net: stm32: add designware mac glue code for stm32</title>
<updated>2017-01-28T19:04:47Z</updated>
<author>
<name>Michael Kurz</name>
<email>michi.kurz@gmail.com</email>
</author>
<published>2017-01-22T15:04:27Z</published>
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<id>urn:sha1:b20b70fcc027a173b61950e9bb4a736557d19697</id>
<content type='text'>
This patch adds glue code required for enabling the designware
mac on stm32f7 devices.

Signed-off-by: Michael Kurz &lt;michi.kurz@gmail.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</content>
</entry>
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