u-boot.git/arch/arm/include, branch v2019.01

Merge tag 'u-boot-imx-20190110' of git://git.denx.de/u-boot-imx

2019-01-10T14:28:16Z

Fixes for 2019.01

ARM: vf610: ddrmc: fix initialization completion detection

2019-01-09T15:27:23Z

The CR80 register has multiple interrupt bits, the code is supposed to check bit 8 but instead uses a logical and. In most cases this probably did not affect real operations since at that stage typically none of the other bits are set. Signed-off-by: Stefan Agner Acked-by: Marcel Ziswiler

ARM: vf610: ddrmc: fix CR138 preprocessor define

2019-01-09T15:27:08Z

According to the data sheet bits 10-8 are PHYDRAM_CK_EN. Fix mask to allow setting PHYDRAM_CK_EN correctly. Signed-off-by: Stefan Agner Acked-by: Marcel Ziswiler Reviewed-by: Lukasz Majewski

ARM: vf610: ddrmc: program Dummy DDRBYTE1/2

2019-01-09T15:19:36Z

The Vybrid reference manual VFXXXRM Rev. 0 10/2016 states in chapter 5.2.6.1 DUMMY PADS (DDR/QuadSPI) that those pads need to be programed for correct operation of DDR. Assume the default DDR pin configuration which seems to work well on a Colibri VF50. Signed-off-by: Stefan Agner

arm: Round the dma_alloc_coherent memory size to cache line aligned

2019-01-09T12:13:31Z

When running usb dwc3 gadget driver, we meet random USB enumeration failure in fastboot. The root cause is a cache coherence issue. When it happens, the ctrl_req in gadget driver is allocated at 0xfe932f40, and the usb_composite_dev (cdev) is allocated at 0xfe932f60. So after we submit the setup request (cache flushed) to USB controller, any accessing to usb_composite_dev variable will cause the cache line refill, then when setup transfer is completed, reading the setup data in ctrl_req will gets old value from cache not from memory. The ctrl_req is allocated by API dma_alloc_coherent, but u-boot don't have cohernet memory. so it still needs cache maintain operations before/after HW accessing. Since the cache flush or invalidate bases on cache line, so when the allocated memory size is not cache line aligned, potentially it may meet such issue. This patch modifies the dma_alloc_coherent API to round the size to cache line aligned. Signed-off-by: Ye Li Reviewed-by: Peng Fan

Merge tag 'u-boot-imx-20190101' of git://www.denx.de/git/u-boot-imx

2019-01-01T15:01:00Z

imx for 2019.01 - introduce support for i.MX8M - fix size limit for Vhybrid / pico boards - several board fixes - w1 driver for MX2x / MX5x

imx8m: ddr: removed unused macros

2019-01-01T13:12:18Z

Remove unused DDRC register macros. Signed-off-by: Peng Fan

drivers: ddr: introduce DDR driver for i.MX8M

2019-01-01T13:12:18Z

Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan

imx: imx8m: add lpddr4 header file

2019-01-01T13:12:18Z

Introduce lpddr4 header file Signed-off-by: Peng Fan

imx: imx8m: clock refactor dram pll part

2019-01-01T13:12:18Z

Refactor dram_pll_init to accept args to configure different pll freq. Introduce dram_enable_bypass and dram_disable_bypass Signed-off-by: Peng Fan