u-boot.git/arch/arm/include, branch v2019.10

fsl-layerscape: Add fsl_esdhc peripheral clock support

2019-09-12T08:30:35Z

Add esdhc peripheral clock support for NXP layerscape platforms: LS1046ARDB, LS1043ARDB, LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB Signed-off-by: Yinbo Zhu Signed-off-by: Priyanka Jain

mmc: Add Aspeed SD controller driver

2019-09-05T07:27:31Z

Add support for the Aspeed SD host controller engine. Signed-off-by: Eddie James Reviewed-by: Cédric Le Goater

clk: aspeed: Add support for SD clock

2019-09-05T07:27:31Z

Add code to enable the SD clock on the ast2500 SoC. Reviewed-by: Cédric Le Goater Signed-off-by: Eddie James

i2c: mxc: add CONFIG_CLK support

2019-09-02T04:35:08Z

When CONFIG_CLK enabled, use CLK UCLASS for clk related settings. Signed-off-by: Peng Fan Reviewed-by: Frieder Schrempf Tested-by: Frieder Schrempf hs: removed hunk in mxc_i2c_probe() as not longer in code

Convert CONFIG_ARCH_CPU_INIT to Kconfig

2019-08-25T23:32:55Z

This converts the following to Kconfig: CONFIG_ARCH_CPU_INIT Signed-off-by: Adam Ford Acked-by: Chris Packham Tested-by: Felix Brack

rockchip: rk3399: derive ethaddr from cpuid

2019-08-23T10:15:31Z

Generate a MAC address based on the cpuid available in the efuse block: Use the first 6 byte of the cpuid's SHA256 hash and set the locally administered bits. Also ensure that the multicast bit is cleared. The MAC address is only generated and set if there is no ethaddr present in the saved environment. This is based off of Klaus Goger's work in 8adc9d Signed-off-by: Rohan Garg Reviewed-by: Kever Yang

armv8: ls1028a: add icid setup for platform devices

2019-08-22T03:37:36Z

Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, edma, qdma, gpu, display and sec. Signed-off-by: Laurentiu Tudor Reviewed-by: Horia Geantă Reviewed-by: Prabhakar Kushwaha

armv8: ls1088a: add icid setup for platform devices

2019-08-22T03:37:36Z

Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, sec. The ICID macros for SEC needed to be adapted because the format of the registers is different. Signed-off-by: Laurentiu Tudor Reviewed-by: Horia Geantă Reviewed-by: Prabhakar Kushwaha

armv8: fsl-layerscape: make icid setup endianness aware

2019-08-22T03:37:36Z

The current implementation assumes that the registers holding the ICIDs are universally big endian. That's no longer the case on newer platforms so update the code to take into account the endianness of each register. Signed-off-by: Laurentiu Tudor Reviewed-by: Horia Geantă Reviewed-by: Prabhakar Kushwaha

armv8: fsl-layerscape: add base addresses for several devices

2019-08-22T03:37:36Z

Add CCSR base addresses for ESDHC2, EDMA QDMA, DISPLAY and GPU devices. Signed-off-by: Laurentiu Tudor Reviewed-by: Prabhakar Kushwaha