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<title>u-boot.git/arch/arm/include, branch v2024.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/include?h=v2024.01</id>
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<updated>2023-11-17T16:58:26Z</updated>
<entry>
<title>Revert "arm64: Use FEAT_HAFDBS to track dirty pages when available"</title>
<updated>2023-11-17T16:58:26Z</updated>
<author>
<name>Chris Packham</name>
<email>judge.packham@gmail.com</email>
</author>
<published>2023-10-27T00:23:54Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0585c28fda1007e4a90dea5f70723cff0b63dd98'/>
<id>urn:sha1:0585c28fda1007e4a90dea5f70723cff0b63dd98</id>
<content type='text'>
This reverts commit 6cdf6b7a340db4ddd008516181de7e08e3f8c213. This is
part of a series trying to make use of the arm64 hardware features for
tracking dirty pages. Unfortunately this series causes problems for the
AC5/AC5X SoCs. Having exhausted other options the consensus seems to be
reverting this series is the best course of action.

Signed-off-by: Chris Packham &lt;judge.packham@gmail.com&gt;
</content>
</entry>
<entry>
<title>Revert "arm64: Use level-2 for largest block mappings when FEAT_HAFDBS is present"</title>
<updated>2023-11-17T16:58:26Z</updated>
<author>
<name>Chris Packham</name>
<email>judge.packham@gmail.com</email>
</author>
<published>2023-10-27T00:23:53Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=eed8294b75a5908a486945ff6655d4dc9aae5fed'/>
<id>urn:sha1:eed8294b75a5908a486945ff6655d4dc9aae5fed</id>
<content type='text'>
This reverts commit 836b8d4b205d2175b57cb9ef271e638b0c116e89. This is
part of a series trying to make use of the arm64 hardware features for
tracking dirty pages. Unfortunately this series causes problems for the
AC5/AC5X SoCs. Having exhausted other options the consensus seems to be
reverting this series is the best course of action.

Signed-off-by: Chris Packham &lt;judge.packham@gmail.com&gt;
</content>
</entry>
<entry>
<title>Revert "armv8: enable HAFDBS for other ELx when FEAT_HAFDBS is present"</title>
<updated>2023-11-17T16:58:26Z</updated>
<author>
<name>Chris Packham</name>
<email>judge.packham@gmail.com</email>
</author>
<published>2023-10-27T00:23:52Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ee23d7466c77d01ee63efb76db2c5fd3b7cdd6f7'/>
<id>urn:sha1:ee23d7466c77d01ee63efb76db2c5fd3b7cdd6f7</id>
<content type='text'>
This reverts commit c1da6fdb5c239b432440721772d993e63cfdeb20. This is
part of a series trying to make use of the arm64 hardware features for
tracking dirty pages. Unfortunately this series causes problems for the
AC5/AC5X SoCs. Having exhausted other options the consensus seems to be
reverting this series is the best course of action.

Signed-off-by: Chris Packham &lt;judge.packham@gmail.com&gt;
</content>
</entry>
<entry>
<title>sunxi: H616: add LPDDR4 DRAM support</title>
<updated>2023-11-12T18:04:32Z</updated>
<author>
<name>Mikhail Kalashnikov</name>
<email>iuncuim@gmail.com</email>
</author>
<published>2023-11-11T09:10:00Z</published>
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<id>urn:sha1:4b02f0120a4bb2a5d7081aef8cef6a4ca57e9db2</id>
<content type='text'>
The H616 SoC family has support for several types of DRAM: DDR3,
LPDDR3, DDR4 and LPDDR4.
At the moment, the driver only supports DDR3 and LPDDR3 memory.
Let's extend the driver to support the LPDDR4 memory. This type
of memory widely used in device with T507(-H) SoC and new orangepi
zero3 with H618.
The compatibility with T507 is not yet complete, because there
is difference in the phy_init array.
The LPDDR4-2133 timings correspond to DRAM Rayson RS1G32LO4D2BDS-53BT
found on the NOR SPI from the Orangepi Zero 3 4GB.

Signed-off-by: Mikhail Kalashnikov &lt;iuncuim@gmail.com&gt;
Tested-by: Piotr Oniszczuk &lt;piotr.oniszczuk@gmail.com&gt;
Reviewed-by: Jernej Skrabec &lt;jernej.skrabec@gmail.com&gt;
Acked-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
</entry>
<entry>
<title>sunxi: mmc: Move header to the driver directory</title>
<updated>2023-11-12T16:45:08Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2023-10-31T05:22:35Z</published>
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<id>urn:sha1:43b573df333c51c435a50e0660522d826d62911e</id>
<content type='text'>
The MMC controller driver is (and ought to be) the only user of these
register definitions. Put them in a header next to the driver to remove
the dependency on a specific ARM platform's headers.

Due to the sunxi_mmc_init() prototype, the file was not renamed. None of
the register definitions were changed.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
Reviewed-by: Jaehoon Chung &lt;jh80.chung@samsung.com&gt;
</content>
</entry>
<entry>
<title>Merge branch '2023-11-10-assorted-fixes'</title>
<updated>2023-11-10T16:01:51Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-11-10T13:44:18Z</published>
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<id>urn:sha1:bb7121f6aa644b72115a24f63d3ee6e52629cc99</id>
<content type='text'>
- Fix some issues Coverity has reported, update MAINTAINERS file,
  another bootstd fix, typo fix in error message, gitignore fix and
  update TI's URL in many places.
</content>
</entry>
<entry>
<title>tree-wide: Replace http:// link with https:// link for ti.com</title>
<updated>2023-11-10T16:01:50Z</updated>
<author>
<name>Nishanth Menon</name>
<email>nm@ti.com</email>
</author>
<published>2023-11-01T20:56:03Z</published>
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<id>urn:sha1:a94a4071d449e12c9fb5ac37d6362d22efcb27da</id>
<content type='text'>
Replace instances of http://www.ti.com with https://www.ti.com

Signed-off-by: Nishanth Menon &lt;nm@ti.com&gt;
</content>
</entry>
<entry>
<title>rockchip: include: asm: fix entering download mode rk3066</title>
<updated>2023-11-10T15:58:56Z</updated>
<author>
<name>Johan Jonker</name>
<email>jbx6244@gmail.com</email>
</author>
<published>2023-10-27T18:35:37Z</published>
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<id>urn:sha1:8ffa9ed295909a638932167486b62ff1adcaa7a3</id>
<content type='text'>
Keep track of the re-entries with help of the lr register.
This binary can be re-used and called from various BROM functions.
Only when it's called from the part that handles SPI, NAND or EMMC
hardware it needs to early return to BROM ones.
In download mode when it handles data on USB OTG and UART0
this section must be skipped.

Unlike newer Rockchip SoC models the rk3066 BROM code does not have built-in
support to enter download mode on return to BROM. This binary must check
the boot mode register for the BOOT_BROM_DOWNLOAD flag and reset if it's set.
It then returns to BROM to the end of the function that reads boot blocks.
From there the BROM code goes into a download mode and waits for data
on USB OTG and UART0.

Signed-off-by: Johan Jonker &lt;jbx6244@gmail.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>mmc: tegra: get default-tap and default-trim from device tree</title>
<updated>2023-11-03T16:37:15Z</updated>
<author>
<name>Svyatoslav Ryhel</name>
<email>clamor95@gmail.com</email>
</author>
<published>2023-10-03T06:33:52Z</published>
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<id>urn:sha1:e1bbc5acefae97661614ba76c745b1d511006f8e</id>
<content type='text'>
Default-tap and default-trim values are used for eMMC setup
mostly on T114+ devices. As for now, those values are hardcoded
for T210 and ignored for all other Tegra generations. Fix this
by passing tap and trim values from dts.

Signed-off-by: Svyatoslav Ryhel &lt;clamor95@gmail.com&gt;
</content>
</entry>
<entry>
<title>arm: armv8: mmu: Prepare for common.h removal</title>
<updated>2023-11-02T10:30:18Z</updated>
<author>
<name>Paul Barker</name>
<email>paul.barker.ct@bp.renesas.com</email>
</author>
<published>2023-11-01T20:05:52Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0a5d5fe30de6602b1ddb2a72e69482c6e6f3d063'/>
<id>urn:sha1:0a5d5fe30de6602b1ddb2a72e69482c6e6f3d063</id>
<content type='text'>
If &lt;common.h&gt; won't be included before &lt;asm/armv8/mmu.h&gt;, we need to
ensure that we have the required type definitions.

Signed-off-by: Paul Barker &lt;paul.barker.ct@bp.renesas.com&gt;
</content>
</entry>
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