u-boot.git/arch/arm/include, branch v2025.04

rockchip: rk3399: grf: Fix enum typos for UART2

2025-02-19T15:06:42Z

In the GRF header file, some instances of UART2 pinmux are prefixed with "GRF_UART2DBG" while others have "GRF_UART2DGB". Since UART2 is the default console UART and used for debugging, it is more likely the name should be UART2DBG. Fix the ones that are wrong. Fixes: a2c08df3813b ("pinctrl: add driver for rk3399") Fixes: fa72de10452c ("rockchip: arm64: rk3399: move grf register definitions to grf_rk3399.h") Signed-off-by: Chen-Yu Tsai Reviewed-by: Quentin Schulz Reviewed-by: Paul Kocialkowski Reviewed-by: Kever Yang

arm64: Add late jump to kernel board hook

2025-02-15T13:44:43Z

Add empty weak assembler function armv8_switch_to_el2_prep() which is jumped to just before U-Boot determines which EL it is running in and decides which path to take to boot the Linux kernel. This weak function is meant to be used by architecture specific code to implement jump to a firmware blob, which then returns right past this weak function and continues execution of U-Boot code which then boots the Linux kernel. One example of such use case is when U-Boot jump tp TFA BL31, which switches from EL3 to EL2 and then returns to U-Boot code newly running in EL2 and starts the Linux kernel. The weak function is called with caches already disabled and DM shut down. Any preparatory work or even loading of more data must be done in board_prep_linux(), this hook is meant only for the final jump to the firmware and return to U-Boot before booting Linux. Reviewed-by: Tom Rini Signed-off-by: Marek Vasut

ARM: tegra210: clock: implement PLLD2 support

2025-02-12T08:35:17Z

PLLD2 is a simple clock (controlled by 2 registers) and appears starting from T30. Primary use of PLLD2 is as main HDMI clock parent. Signed-off-by: Svyatoslav Ryhel

ARM: tegra124: clock: implement PLLD2 support

2025-02-12T08:35:17Z

PLLD2 is a simple clock (controlled by 2 registers) and appears starting from T30. Primary use of PLLD2 is as main HDMI clock parent. Signed-off-by: Svyatoslav Ryhel

sunxi: clock: improve grouping of default clock register values

2025-01-22T22:44:34Z

With each new SoC added to the clock_sun50i_h6.h header file, we add a list of default values for the bus clock registers. This list gets a bit hard to read, as the spacing between the lines looks confusing. Tighten the lines by removing empty lines, to make it more obvious which values belong together. Also remove those comments that were more or less duplicating the next code line, and didn't add any information. This makes it easier to find existing values and to add support for new SoCs. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec

arm64: Add MIDR entries for Cortex-A57 and Cortex-A76

2025-01-12T22:49:58Z

Add MIDR entries for Cortex-A57 and Cortex-A76 cores. Those are used on R-Car Gen3 and Gen4 SoCs respectively. Reviewed-by: Paul Barker Reviewed-by: Peter Robinson Signed-off-by: Marek Vasut

arm64: Convert core type check macros into inline functions

2025-01-12T22:49:58Z

Turn the core type check macros into inline functions to perform better type checking on them. The inline functions get optimized out in case they are not used. Indent the MIDR_PARTNUM_CORTEX_An macros in preparation for addition of future three-digit cores and use MIDR_PARTNUM_SHIFT in MIDR_PARTNUM_MASK to be consistent. Reviewed-by: Paul Barker Reviewed-by: Peter Robinson Signed-off-by: Marek Vasut

clk: rockchip: rk3588: fix mask define for aclk_vop_root

2025-01-11T00:56:22Z

The mask for aclk_vop_root is 3-bit wide, not 2-bit wide according to the TRM, so set the mask accordingly. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Reviewed-by: Kever Yang

imx: Use per board ddrphy_trained_csr

2024-12-23T11:10:15Z

Drop global ddrphy_trained_csr which maybe different with per board ddrphy_trained_csr. DDR TOOL generates ddrphy_trained_csr for each board, using the global ddrphy_trained_csr has risk that values may be not up to date. Signed-off-by: Peng Fan

imx: Add iMX91 support

2024-12-07T12:07:04Z

iMX91 is reduced part from iMX93 with part number: i.MX9131/11/01 It removed A55_1, M33, MIPI DSI, LVDS, etc. i.MX9131: - Support 2.4GT/s DDR and HWFFC at 1.2GT/s i.MX9121: - A55 at 800Mhz and DDR at 1600MTS, with low drive mode. i.MX9111: - Support 1.6GT/s DDR and HWFFC at 800MT/s i.MX9101: - Support 800Mhz ARM clock - Support 1.6GT/s DDR and HWFFC at 800MT/s - No parallel display, eQOS, flexcan Updated Clock/Container/CPU and etc for i.MX91 Signed-off-by: Ye Li Signed-off-by: Peng Fan