u-boot.git/arch/arm/include, branch v2026.04

armv7: ls102xa: fix SPI flash clock

2026-03-23T06:27:24Z

Commit bb6f3c0f7634 ("armv7: ls102xa: Update SCFG_QSPI_CLKSEL value") broke the SPI boot on the LS1021ATSN board (ls1021atsn_qspi_defconfig) at least. The commit message reads Update SCFG_QSPI_CLKSEL value : 0xC -> 0x5 which means ClusterPLL/16 The original submitted patch had the following description: Value 0xC is reserved. Replace it with correct value 0x5 which is ClusterPLL/16 Unfortunatly, the little information which was there, was stripped even further. Why is 0x5 the "correct" value? In fact, it seems that the upper bit is just ignored and thus the value 0xC translates to 0x4 which is ClusterPLL/20. This, will result in a SPI clock of 60MHz (if the PLL is clocked at 1.2GHz). But even that is too much for the (default) 03h read opcode (max 50MHz). Set the value to ClusterPLL/24 which is 50MHz. Link: https://lore.kernel.org/r/1568804284-25162-1-git-send-email-kuldeep.singh@nxp.com/ Fixes: bb6f3c0f7634 ("armv7: ls102xa: Update SCFG_QSPI_CLKSEL value") Signed-off-by: Michael Walle Reviewed-by: Vladimir Oltean Signed-off-by: Peng Fan

treewide: Remove Timesys from ADI ADSP maintenance

2026-03-04T20:25:27Z

After years of developing the ADI ADSP platform, Timesys was purchased by another company and is no longer contracted to maintain the platform. Signed-off-by: Philip Molloy Reviewed-by: Greg Malysa

sunxi: clock: H6: add NAND controller clock registers

2026-02-03T20:45:11Z

Add missing NAND controller-related clock registers The NAND controller on H6/H616 uses one clock for its internal logic (NAND0_CLK) and one clock for ECC engine (NAND1_CLK) in addition to AHB and MBUS clocks. As NAND{0,1}_CLKs and MBUS_GATE are missing, add them. The bit locations are from H616/H6 User Manual. Signed-off-by: Richard Genoud Signed-off-by: Michael Trimarchi

mtd: rawnand: sunxi: remove usage of struct sunxi_ccm_reg

2026-02-03T20:44:33Z

The sunxi_ccm_reg is legacy, drop its usage from nand related code For that, CCU_NAND0_CLK_CFG and CCU_AHB_GATE1 are added to the clock files when missing. And clock code in sunxi_nand{,_spl}.c and board.c are changed to use the new scheme. Moreover, drop AHB_DIV_1 in favor of the more readable CCM_NAND_CTRL_M/N Suggested-by: Andre Przywara Signed-off-by: Richard Genoud Signed-off-by: Michael Trimarchi

sunxi: dram: detect non-power-of-2 sized DRAM chips

2026-01-25T23:29:32Z

Some boards feature an "odd" DRAM size, where the total RAM is 1.5GB or 3GB. Our existing DRAM size detection routines can only detect power-of-2 sized configuration, and on those boards the DRAM size is overestimated, so this typically breaks the boot quite early. There doesn't seem to be an easy explicit way to detect those odd-sized chips, but we can test whether the later part of the memory behaves like memory, by verifying that a written pattern can be read back. Experiments show that there is no aliasing effect here, as all locations in the unimplemented range always return some fixed pattern, and cannot be changed. Also so far all those boards use a factor of 3 of some lower power-of-2 number, or 3/4th of some higher number. The size detection routine discovers the higher number, so we can check for some memory cells beyond 75% of the detected size to be legit. Add a routine the inverts all bits at a given location in memory, and reads that back to prove that the new value was stored. Then test the memory cell at exactly 3/4th of the detected size, and cap the size of the memory to 75% when this test fails. For good measure also make sure that memory just below the assumed memory end really works. This enables boards which ship with such odd memory sizes. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec

misc: ele_api: Add Voltage change start and finish APIs

2026-01-17T18:00:23Z

On GDET enabled part, need to call voltage change start and finish APIs when adjust the voltage more than 100mv. Otherwise GDET will be triggered and system is reset Reviewed-by: Peng Fan Signed-off-by: Ye Li Signed-off-by: Peng Fan

arm: mediatek: remove extra gpio header

2026-01-16T15:53:57Z

Remove empty gpio.h header file and CONFIG_GPIO_EXTRA_HEADER on ARCH_MEDIATEK. There is no reason to have these since the header doesn't contain anything. Signed-off-by: David Lechner Reviewed-by: Quentin Schulz

Merge tag 'u-boot-amlogic-next-20251219' of https://source.denx.de/u-boot/custodians/u-boot-amlogic into next

2025-12-19T16:30:26Z

- Add u-boot SPL support for GX SoCs - meson_gx_mmc: reduce maximum frequency - Add support for EFI capsule updates on all Amlogic boards

rockchip: sdram: Add rockchip_sdram_type() helper

2025-12-13T16:02:10Z

Add a helper function based on rockchip_sdram_size() that return what DRAM type is used on current running board. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang

arm: meson: add support for EFI capsule updates

2025-12-11T16:27:15Z

Previously, few Amlogic devices supported EFI capsule updates. Generally only the Libre Computer ones with SPI flash supported it, thanks to board-specific code. This commit commonises capsule update support across supported Amlogic boards. Similar to Qualcomm's support for it, the dfu string and firmware name is automatically generated at runtime depending on which device we are booted from. Right now this supports flashing to the eMMC/SD and SPI flash. As usual, the capsule UUID is automatically generated. You can get it by enabling CONFIG_CMD_EFIDEBUG and running: => efidebug capsule esrt ======================================== ESRT: fw_resource_count=1 ESRT: fw_resource_count_max=1 ESRT: fw_resource_version=1 [entry 0]============================== ESRT: fw_class=796180D4-AAB2-50F1-B16A-53DFF9CA89B2 ESRT: fw_type=unknown ESRT: fw_version=0 ESRT: lowest_supported_fw_version=0 ESRT: capsule_flags=0 ESRT: last_attempt_version=0 ESRT: last_attempt_status=success ======================================== Reviewed-by: Evgeny Bachinin Reviewed-by: Neil Armstrong Signed-off-by: Ferass El Hafidi Link: https://patch.msgid.link/20251211-meson-capsule-v4-1-59f126ba4115@postmarketos.org Signed-off-by: Neil Armstrong