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<title>u-boot.git/arch/arm/lib/Makefile, branch v2023.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/lib/Makefile?h=v2023.01</id>
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<updated>2022-09-14T19:23:03Z</updated>
<entry>
<title>Add in the ability to load and boot an uncompressed kernel image during the Falcon Mode boot sequence.</title>
<updated>2022-09-14T19:23:03Z</updated>
<author>
<name>Nathan Barrett-Morrison</name>
<email>nathan.morrison@timesys.com</email>
</author>
<published>2022-02-02T20:05:18Z</published>
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<id>urn:sha1:7a0d88076b9cd8ccc88d41383f92ac2494d4168e</id>
<content type='text'>
This is required for architectures which do not support compressed kernel images (i.e. ARM64).  This is only used while not booting via FIT image.

Signed-off-by: Nathan Barrett-Morrison &lt;nathan.morrison@timesys.com&gt;
Cc: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>ARM: cache: Allow SPL to build cache-pl310.c</title>
<updated>2022-09-01T21:18:42Z</updated>
<author>
<name>Philip Oberfichtner</name>
<email>pro@denx.de</email>
</author>
<published>2022-08-17T13:07:13Z</published>
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<id>urn:sha1:b6664eace8a26f0850ffa0a3e349ca2ffa960f2a</id>
<content type='text'>
Introduce the new Kconfig symbol CONFIG_SPL_SYS_L2_PL310 to allow the
SPL to build cache-pl310.c.

Before this commit, the SPL could enable the PL310 L2 cache [1], but the
cache maintenance functions from cache-pl310.c were only useable for
non-SPL builds.

After enabling the cache one must be able to flush it, too. Thus this
commit allows cache-pl310.c to be included in the SPL build.

[1] See for example arch/arm/mach-imx/cache.c: v7_outer_cache_enable()

Signed-off-by: Philip Oberfichtner &lt;pro@denx.de&gt;
</content>
</entry>
<entry>
<title>arm: init: save previous bootloader data</title>
<updated>2022-04-04T18:53:26Z</updated>
<author>
<name>Dzmitry Sankouski</name>
<email>dsankouski@gmail.com</email>
</author>
<published>2022-02-22T18:49:52Z</published>
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<id>urn:sha1:12a3e1ada06c702c403cf1eebb063ef7a34688cd</id>
<content type='text'>
When u-boot is used as a chain-loaded bootloader (replacing OS kernel),
previous bootloader leaves data in RAM, that can be reused.

For example, on recent arm linux system, when chainloading u-boot,
there are initramfs and fdt in RAM prepared for OS booting. Initramfs
may be modified to store u-boot's payload, thus providing the ability to
use chainloaded u-boot to boot OS without any storage support.

Two config options added:
- SAVE_PREV_BL_INITRAMFS_START_ADDR
  saves initramfs start address to 'prevbl_initrd_start_addr' environment
  variable
- SAVE_PREV_BL_FDT_ADDR
  saves fdt address to 'prevbl_fdt_addr' environment variable

Signed-off-by: Dzmitry Sankouski &lt;dsankouski@gmail.com&gt;
Cc: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>spl: Add semihosting boot method</title>
<updated>2022-04-01T19:03:13Z</updated>
<author>
<name>Sean Anderson</name>
<email>sean.anderson@seco.com</email>
</author>
<published>2022-03-22T20:59:19Z</published>
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<id>urn:sha1:8e1c9fe243a31a0b0a40a80cc20fc3c06246d675</id>
<content type='text'>
This adds a boot method for loading the next stage from the host. It is
mostly modeled off of spl_load_image_ext. I am not really sure why/how
spl_load_image_fat uses three different methods to load the image, but
the simple case seems to work OK for now.

To control the presence of this boot method, we add a config symbol.
While we're at it, we update the original semihosting config symbol.

I think semihosting has some advantages of other forms of JTAG boot.
Common other ways to boot from JTAG include:

- Implementing DDR initialization through JTAG (typically with dozens of
  lines of TCL) and then loading U-Boot. The DDR initialization
  typically uses hard-coded register writes, and is not easily adapted
  to different boards. BOOT_DEVICE_SMH allows booting with SPL,
  leveraging U-Boot's existing DDR initialization code. This is the
  method used by NXP's CodeWarrior IDE on Layerscape processors (see
  AN12270).
- Loading a bootloader into SDRAM, waiting for it to initialize DDR, and
  then loading U-Boot. This is tricky, because the debugger must stop the
  boot after the bootloader has completed its work. Trying to load
  U-Boot too early can cause failure to boot. This is the method used by
  Xilinx with its Zynq(MP) processors.
- Loading SPL with BOOT_DEVICE_RAM and breaking before SPL loads the
  image to load U-Boot at the appropriate place. This can be a bit
  tricky, because the load address is dependent on the header size. An
  elf with symbols must also be used in order to stop at the appropriate
  point. BOOT_DEVICE_SMH can be viewed as an extension of this process,
  where SPL automatically stops and tells the host where to place the
  image.

Signed-off-by: Sean Anderson &lt;sean.anderson@seco.com&gt;
</content>
</entry>
<entry>
<title>arm64: arch/arm/lib: Add optimized memset/memcpy/memmove functions</title>
<updated>2021-09-24T11:48:06Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2021-09-02T15:00:17Z</published>
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<id>urn:sha1:dbf6b14e0a388330b0a0cb472e1bd5c8b5d711a4</id>
<content type='text'>
Ported from https://github.com/ARM-software/optimized-routines

These files are included from this repository, including the latest
git commit ID:
string/aarch64/memcpy.S: afd6244a1f8d
string/aarch64/memset.S: e823e3abf5f8
string/asmdefs.h: e823e3abf5f8

Note that memmove is also handled by the memcpy function.

Please note that when adding these optimized functions as default memset
memcpy functions in U-Boot, U-Boot fails to boot on the LX2160ARDB.
After the initial ATF output, no U-Boot output is shown on the serial
console. Some exception is triggered here in the very early boot process
as some of the assembler opcodes need the caches to be enabled.

Because of this, a follow-up patch will add a check to use a simple
non-optimized memset for the "cache disabled" case.

Note:
I also integrated and tested with the Linux versions of these optimized
functions. They are similar to the ones now integrated but these ARM
versions are still a small bit faster.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>ARM: make LTO available</title>
<updated>2021-05-24T18:21:30Z</updated>
<author>
<name>Marek Behún</name>
<email>marek.behun@nic.cz</email>
</author>
<published>2021-05-20T11:24:22Z</published>
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<id>urn:sha1:8f9696510afc2b52ebeba5d1db4883cf3331c206</id>
<content type='text'>
Make LTO available for ARM architecture.

Signed-off-by: Marek Behún &lt;marek.behun@nic.cz&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>ARM: fix LTO build for some thumb-interwork cases</title>
<updated>2021-05-24T18:21:30Z</updated>
<author>
<name>Marek Behún</name>
<email>marek.behun@nic.cz</email>
</author>
<published>2021-05-20T11:24:11Z</published>
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<id>urn:sha1:e5fc9037dd3391a63cf6f6f7da015507ae12158d</id>
<content type='text'>
Fix LTO build for some thumb-interwork usecases (such as for
da850evm_defconfig), where inline assmebly such as
  mrc p15,0,r2,c1,c0,0
causes the compiler to fail during LTO linking with
  Error: selected processor does not support `mrc p15,0,r2,c1,c0,0'
         in Thumb mode

Signed-off-by: Marek Behún &lt;marek.behun@nic.cz&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>bdinfo: arm: Move ARM-specific info into its own file</title>
<updated>2020-06-25T17:24:12Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-05-10T20:16:56Z</published>
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<id>urn:sha1:59b0d7d839f135bc44d3459784337a657149f8b3</id>
<content type='text'>
We don't really want to have ARM-specific code in a generic file. Create
a new arch-specific function to hold it, and move it into that.

Make the function weak so that any arch can implement it.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>ARM: reset: use do_reset in SPL/TPL if SYSRESET was not enabled for them</title>
<updated>2020-05-01T11:46:22Z</updated>
<author>
<name>Claudius Heine</name>
<email>ch@denx.de</email>
</author>
<published>2020-03-04T14:23:10Z</published>
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<id>urn:sha1:b46e6cc581b3dcb48cdd96bd5db0c40c86285975</id>
<content type='text'>
In case CONFIG_SYSRESET is set, do_reset from reset.c will not be available
anywere, even if SYSRESET is disabled for SPL/TPL.

'do_reset' is called from SPL for instance from the panic handler and
PANIC_HANG is not set

Signed-off-by: Claudius Heine &lt;ch@denx.de&gt;
Reviewed-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
</entry>
<entry>
<title>arch: arm: Program GIC LPI configuration table</title>
<updated>2020-01-10T19:18:26Z</updated>
<author>
<name>Bharat Kumar Reddy Gooty</name>
<email>bharat.gooty@broadcom.com</email>
</author>
<published>2019-12-16T17:09:43Z</published>
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<id>urn:sha1:0bc4356deae7ff2de2441fc519f395e75bed8923</id>
<content type='text'>
Programs the following:
1. Redistributor PROCBASER configuration table (which
is common for all redistributors)
2. Redistributor pending table (PENDBASER), for all the
available redistributors.

Signed-off-by: Bharat Kumar Reddy Gooty &lt;bharat.gooty@broadcom.com&gt;
Signed-off-by: Vladimir Olovyannikov &lt;vladimir.olovyannikov@broadcom.com&gt;
</content>
</entry>
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