u-boot.git/arch/arm/lib/cache-cp15.c, branch v2015.10

ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching

2015-04-16T12:59:33Z

The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being properly set to allow for the configuration specified caching modes to be active over DRAM. This commit fixes those issues. Signed-off-by: Bryan Brinsko

ARM: cache-cp15: Use more accurate types

2014-11-12T06:25:42Z

size_t is the canonical type to represent variables that contain a size. Use it instead of signed integer. Physical addresses can be larger than 32-bit, so use a more appropriate type for them as well. phys_addr_t is a type that is 32-bit on systems that use 32-bit addresses and 64-bit if the system is 64-bit or uses a form of physical address extension to use a larger address space on 32-bit systems. Using these types the same API can be implemented on a wider range of systems. Signed-off-by: Thierry Reding

arm: cache: Add support for write-allocate D-Cache

2014-10-06T15:40:21Z

Add configuration for the write-allocate mode of L1 D-Cache on ARM. This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA . Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek

ARM: Fix overflow in MMU setup

2014-08-30T11:46:39Z

The patch fixes a corner case where adding size to DRAM start resulted in a value (1 << 32), which in turn overflew the u32 computation, which resulted in 0 and it therefore prevented correct setup of the MMU tables. The addition of DRAM bank start and it's size can end up right at the end of the address space in the special case of a machine with enough memory. To prevent this overflow, shift the start and size separately and add them only after they were shifted. Hopefully, we only have systems in tree which have DRAM size aligned to 1MiB boundary. If not, this patch would break such systems. On the other hand, such system would be broken by design anyway. Signed-off-by: Marek Vasut Cc: Albert ARIBAUD

ARM: cache_v7: use __weak

2014-07-04T17:57:22Z

This is not only more readable but also prevents a warning about a missing prototype. The prototypes which are actually missing are added. cc: Albert Aribaud Signed-off-by: Jeroen Hofstee Reviewed-by: Tom Rini

Add GPL-2.0+ SPDX-License-Identifier to source files

2013-07-24T13:44:38Z

Signed-off-by: Wolfgang Denk [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini

ARM: mmu: Set domain permissions to client access

2013-03-28T08:10:58Z

The 'XN' execute never bit is set in the pagetables. This will prevent speculative prefetches to non executable regions. But the domain permissions are set as master in the DACR register. So the pagetable attribute for 'XN' is not effective. Change the permissions to client. This fixes lot of speculative prefetch aborts seen on OMAP5 secure devices. Signed-off-by: R Sricharan Tested-by: Vincent Stehle Cc: Vincent Stehle Cc: Tom Rini Cc: Albert ARIBAUD

ARM: mmu: Introduce weak dram_bank_setup function

2013-03-28T08:06:49Z

Introduce a weak version of dram_bank_setup function to allow a platform specific function. This is used in the subsequent patch to setup dram region without 'XN' attribute in order to enable the region under client permissions. Signed-off-by: R Sricharan Cc: Vincent Stehle Cc: Tom Rini Cc: Albert ARIBAUD

arm: Move tlb_addr and tlb_size to arch_global_data

2013-02-01T20:21:58Z

Move these fields into arch_global_data and tidy up. Signed-off-by: Simon Glass [trini: Address tlb_size in this patch as well] Signed-off-by: Tom Rini

arm: move flush_dcache_all() to just before disable cache

2013-01-10T21:21:27Z

In Cortex-A15 architecture, when we run cache invalidate the cache clean operation executes automatically. So if there are any dirty cache lines before disabling the L2 cache these will be synchronized with the main memory when invalidate_dcache_all() runs in the last part of U-boot The two functions after flush_dcache_all is using the stack. So this data will be on the cache. After disable when invalidate is called the data will be flushed from cache to memory. This corrupts the stack in invalida_dcache_all. So this change is required to avoid the u-boot hang. So flush has to be done just before clearing CR_C bit Signed-off-by: Arun Mankuzhi Signed-off-by: Simon Glass