u-boot.git/arch/arm/lib/cache-cp15.c, branch v2018.03

ARM: remove bogus cp_delay() function

2017-06-12T12:38:39Z

The cp_delay() function was introduced because of a missing 'volatile' attribute to the 'asm' statement in get_cr() which led to the 'mrc' instruction in get_cr() being optimised out eventually. This has been fixed in commit 53fd4b8c22bb ("arm: mmu: Add missing volatile for reading SCTLR register") but the bogus cp_delay() function which was introduced as a workaround for the malfunctioning get_cr() was never removed. Signed-off-by: Lothar Waßmann

arm: Disable LPAE if not enabled

2017-06-09T19:39:32Z

If CONFIG_ARMV7_LPAE is not defined we should make sure that the feature is disabled. This can happen if U-Boot is chain-loaded from another boot loader which does enable LPAE. Signed-off-by: Simon Glass

arm: Don't try to support CONFIG_ARMV7_LPAE on ARMv4T

2017-06-09T19:39:32Z

At present if CONFIG_ARMV7_LPAE is defined then mmu_setup() will use instructions which are invalid on ARMv4T. This happens on Tegra since it has an ARMv4T boot CPU. Add a check for the architecture version to allow the code to be built. It will not actually be executed by the boot CPU, but needs to compile. Signed-off-by: Simon Glass

arm: Rename HCTR to HTCR

2017-06-09T19:39:31Z

This appears to be a typo. Fix it. Signed-off-by: Simon Glass

arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode

2016-11-13T20:54:36Z

While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver. Fix this to mark the regions as XN by default. Signed-off-by: Keerthy Reviewed-by: Alexander Graf Reviewed-by: Tom Rini

arm: print the cache config option in hex instead of decimal

2016-11-13T20:54:36Z

Printing the option value in hex makes it more comprehensible. Signed-off-by: Keerthy Reviewed-by: Tom Rini

arm: cache: always flush cache line size for page table

2016-08-26T21:04:56Z

The page table is maintained by the CPU, hence it is safe to always align cache flush to a whole cache line size. This allows to use mmu_page_table_flush for a single page table, e.g. when configure only small regions through mmu_set_region_dcache_behaviour. Signed-off-by: Stefan Agner Tested-by: Fabio Estevam Reviewed-by: Simon Glass Reviewed-by: Heiko Schocher

arm: cache: add support for LPAE for region D$ behavior

2016-08-26T21:04:56Z

Add LPAE support for mmu_set_region_dcache_behaviour. The function is in use in some LPAE capable board such TI DRA7xx or NXP i.MX 7. Signed-off-by: Stefan Agner

arm: Add support for HYP mode and LPAE page tables

2016-03-27T13:12:17Z

We currently always modify the SVC versions of registers and only support the short descriptor PTE format. Some boards however (like the RPi2) run in HYP mode. There, we need to modify the HYP version of system registers and HYP mode only supports the long descriptor PTE format. So this patch introduces support for both long descriptor PTEs and HYP mode registers. Signed-off-by: Alexander Graf

arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7

2016-01-31T15:32:56Z

The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is set, it configures TTBR0 register. This register must be configured for the cache on ARMv7 to operate correctly. The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor issues which are hard to replicate, for example certain USB sticks are not detected or QSPI NOR sometimes fails to write pages completely. The solution is to replace CONFIG_ARMV7 test with CONFIG_CPU_V7 one. This is correct because the code which added the test(s) for CONFIG_ARMV7 was added shortly after CONFIG_ARMV7 was replaced by CONFIG_CPU_V7 and this code was not adjusted correctly to reflect that change. Signed-off-by: Marek Vasut Cc: Tom Rini Cc: Albert Aribaud Cc: Simon Glass