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<title>u-boot.git/arch/arm/lib/cache.c, branch v2015.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/lib/cache.c?h=v2015.01</id>
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<updated>2014-12-18T20:19:21Z</updated>
<entry>
<title>ARM: Implement non-cached memory support</title>
<updated>2014-12-18T20:19:21Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-12-10T05:25:22Z</published>
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<id>urn:sha1:1dfdd9ba4e699562a3b282f4fb5efe4c80e6e8c7</id>
<content type='text'>
Implement an API that can be used by drivers to allocate memory from a
pool that is mapped uncached. This is useful if drivers would otherwise
need to do extensive cache maintenance (or explicitly maintaining the
cache isn't safe).

The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting.
Boards can set this to the size to be used for the non-cached area. The
area will typically be right below the malloc() area, but architectures
should take care of aligning the beginning and end of the area to honor
any mapping restrictions. Architectures must also ensure that mappings
established for this area do not overlap with the malloc() area (which
should remain cached for improved performance).

While the API is currently only implemented for ARM v7, it should be
generic enough to allow other architectures to implement it as well.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: remove CONFIG_ARM1136 defines</title>
<updated>2014-11-20T16:28:25Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2014-11-06T05:59:37Z</published>
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<id>urn:sha1:3fd968e9314942f2840f8f9fda98079cc0d82288</id>
<content type='text'>
CONFIG_CPU_ARM1136 was introduced into Kconfig by commit 2e07c249a67e
(kconfig: arm: introduce symbol for ARM CPUs).

This commit removes all the defines of CONFIG_ARM1136 and replaces
the only reference in arch/arm/lib/cache.c with CONFIG_CPU_ARM1136.

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
</content>
</entry>
<entry>
<title>ARM: remove CONFIG_ARM926EJS defines</title>
<updated>2014-11-20T16:28:25Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2014-11-06T05:59:36Z</published>
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<id>urn:sha1:5d7b131d41d8a8fb50edf27d945703e757ed8357</id>
<content type='text'>
CONFIG_CPU_ARM926EJS was introduced into Kconfig by commit 2e07c249a67e
(kconfig: arm: introduce symbol for ARM CPUs).

This commit removes all the defines of CONFIG_ARM926EJS and replaces
the only reference in arch/arm/lib/cache.c with CONFIG_CPU_ARM926EJS.

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
</content>
</entry>
<entry>
<title>ARM: cache_v7: use __weak</title>
<updated>2014-07-04T17:57:22Z</updated>
<author>
<name>Jeroen Hofstee</name>
<email>jeroen@myspectrum.nl</email>
</author>
<published>2014-06-23T20:07:04Z</published>
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<id>urn:sha1:fcfddfd50472d7ce84ef4e2853242bbeb7b37325</id>
<content type='text'>
This is not only more readable but also prevents a warning
about a missing prototype. The prototypes which are actually
missing are added.

cc: Albert Aribaud &lt;albert.u.boot@aribaud.net&gt;
Signed-off-by: Jeroen Hofstee &lt;jeroen@myspectrum.nl&gt;
Reviewed-by: Tom Rini &lt;trini@ti.com&gt;
</content>
</entry>
<entry>
<title>arm1136: move cache code from start.S to cache.c</title>
<updated>2014-05-15T14:24:26Z</updated>
<author>
<name>Albert ARIBAUD</name>
<email>albert.u.boot@aribaud.net</email>
</author>
<published>2014-04-15T14:13:47Z</published>
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<id>urn:sha1:b4ee1491b917951c0f57e18fd816a4211f5829d4</id>
<content type='text'>
arch/arm/cpu/arm1136/start.S contain a cache flushing function.
Remove the function and move its code into arch/arm/lib/cache.c.

Signed-off-by: Albert ARIBAUD &lt;albert.u.boot@aribaud.net&gt;
</content>
</entry>
<entry>
<title>Add GPL-2.0+ SPDX-License-Identifier to source files</title>
<updated>2013-07-24T13:44:38Z</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2013-07-08T07:37:19Z</published>
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<id>urn:sha1:1a4596601fd395f3afb8f82f3f840c5e00bdd57a</id>
<content type='text'>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
</content>
</entry>
<entry>
<title>arm: Remove OMAP2420H4 and all omap24xx support</title>
<updated>2013-06-10T12:43:19Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@ti.com</email>
</author>
<published>2013-06-04T12:02:06Z</published>
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<id>urn:sha1:7f5eef93af92ed9efed7867d24b03fd6056a7404</id>
<content type='text'>
The omap2420H4 was the only mainline omap24xx board.  Prior to being
fixed by Jon Hunter in time for v2013.04 it had been functionally broken
for a very long time.  Remove this board as there's not been interest in
it in U-Boot for quite a long time.

Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
</content>
</entry>
<entry>
<title>arm: do not force d-cache enable on all boards</title>
<updated>2011-09-04T09:36:16Z</updated>
<author>
<name>Aneesh V</name>
<email>aneesh@ti.com</email>
</author>
<published>2011-08-16T04:33:05Z</published>
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<id>urn:sha1:cba4b1809f043bf85c806e5a4e342f62bd5ded45</id>
<content type='text'>
c2dd0d45540397704de9b13287417d21049d34c6 added dcache_enable()
to board_init_r(). This enables d-cache for all ARM boards.
As a result some of the arm boards that are not cache-ready
are broken. Revert this change and allow platform code to
take the decision on d-cache enabling.

Also add some documentation for cache usage in ARM.

Signed-off-by: Aneesh V &lt;aneesh@ti.com&gt;
</content>
</entry>
<entry>
<title>arm: minor fixes for cache and mmu handling</title>
<updated>2011-07-04T08:55:25Z</updated>
<author>
<name>Aneesh V</name>
<email>aneesh@ti.com</email>
</author>
<published>2011-06-16T23:30:50Z</published>
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<id>urn:sha1:e05f00792b71184428fdb34a303644a1e457f000</id>
<content type='text'>
1. make sure that page table setup is not done multiple times
2. flush_dcache_all() is more appropriate while disabling cache
   than a range flush on the entire memory(flush_cache())

   Provide a default implementation for flush_dcache_all()
   for backward compatibility and to avoid build issues.

Signed-off-by: Aneesh V &lt;aneesh@ti.com&gt;
</content>
</entry>
<entry>
<title>armv7: integrate cache maintenance support</title>
<updated>2011-07-04T08:55:25Z</updated>
<author>
<name>Aneesh V</name>
<email>aneesh@ti.com</email>
</author>
<published>2011-06-16T23:30:49Z</published>
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<id>urn:sha1:c2dd0d45540397704de9b13287417d21049d34c6</id>
<content type='text'>
- Enable I-cache on bootup
- Enable MMU and D-cache immediately after relocation
	- Do necessary initialization before enabling d-cache and MMU
- Changes to cleanup_before_linux()
	- Make changes according to the new framework

Signed-off-by: Aneesh V &lt;aneesh@ti.com&gt;
</content>
</entry>
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