<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/arch/arm/lib/cache.c, branch v2016.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>ARM: Move SYS_CACHELINE_SIZE over to Kconfig</title>
<updated>2016-08-26T21:04:46+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-08-22T12:22:17+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=067716bac59716b07f1ee70d9bf6e5528289bb45'/>
<id>067716bac59716b07f1ee70d9bf6e5528289bb45</id>
<content type='text'>
This series moves the CONFIG_SYS_CACHELINE_SIZE.  First, in nearly all
cases we are mirroring the values used by the Linux Kernel here.  Also,
so long as (and in this case, it is true) we implement flushes in hunks
that are no larger than the smallest implementation (and given that we
mirror the Linux Kernel, again we are fine) it is OK to align higher.
The biggest changes here are that we always use 64 bytes for CPU_V7 even
if for example the underlying core is only 32 bytes (this mirrors
Linux).  Second, we say ARM64 uses 64 bytes not 128 (as found in the
Linux Kernel) as we do not need multi-platform support (to this degree)
and only the Cavium ThunderX 88xx series has a use for such large
alignment.

Cc: Albert Aribaud &lt;albert.u.boot@aribaud.net&gt;
Cc: Marek Vasut &lt;marex@denx.de&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Cc: Prafulla Wadaskar &lt;prafulla@marvell.com&gt;
Cc: Luka Perkov &lt;luka.perkov@sartura.hr&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Cc: Nagendra T S &lt;nagendra@mistralsolutions.com&gt;
Cc: Vaibhav Hiremath &lt;hvaibhav@ti.com&gt;
Acked-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
Cc: Steve Rae &lt;steve.rae@raedomain.com&gt;
Cc: Igor Grinberg &lt;grinberg@compulab.co.il&gt;
Cc: Nikita Kiryanov &lt;nikita@compulab.co.il&gt;
Cc: Stefan Agner &lt;stefan.agner@toradex.com&gt;
Acked-by: Heiko Schocher &lt;hs@denx.de&gt;
Cc: Mateusz Kulikowski &lt;mateusz.kulikowski@gmail.com&gt;
Cc: Peter Griffin &lt;peter.griffin@linaro.org&gt;
Acked-by: Paul Kocialkowski &lt;contact@paulk.fr&gt;
Cc: Anatolij Gustschin &lt;agust@denx.de&gt;
Acked-by: "Pali Rohár" &lt;pali.rohar@gmail.com&gt;
Cc: Adam Ford &lt;aford173@gmail.com&gt;
Cc: Steve Sakoman &lt;sakoman@gmail.com&gt;
Cc: Grazvydas Ignotas &lt;notasas@gmail.com&gt;
Cc: Nishanth Menon &lt;nm@ti.com&gt;
Cc: Stephen Warren &lt;swarren@wwwdotorg.org&gt;
Cc: Robert Baldyga &lt;r.baldyga@samsung.com&gt;
Cc: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
Cc: Thomas Weber &lt;weber@corscience.de&gt;
Cc: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Cc: David Feng &lt;fenghua@phytium.com.cn&gt;
Cc: Alison Wang &lt;b18965@freescale.com&gt;
Cc: Michal Simek &lt;michal.simek@xilinx.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: York Sun &lt;york.sun@nxp.com&gt;
Cc: Shengzhou Liu &lt;Shengzhou.Liu@nxp.com&gt;
Cc: Mingkai Hu &lt;mingkai.hu@nxp.com&gt;
Cc: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
Cc: Aneesh Bansal &lt;aneesh.bansal@freescale.com&gt;
Cc: Saksham Jain &lt;saksham.jain@nxp.com&gt;
Cc: Qianyu Gong &lt;qianyu.gong@nxp.com&gt;
Cc: Wang Dongsheng &lt;dongsheng.wang@nxp.com&gt;
Cc: Alex Porosanu &lt;alexandru.porosanu@freescale.com&gt;
Cc: Hongbo Zhang &lt;hongbo.zhang@nxp.com&gt;
Cc: tang yuantian &lt;Yuantian.Tang@freescale.com&gt;
Cc: Rajesh Bhagat &lt;rajesh.bhagat@nxp.com&gt;
Cc: Josh Wu &lt;josh.wu@atmel.com&gt;
Cc: Bo Shen &lt;voice.shen@atmel.com&gt;
Cc: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
Cc: Hannes Schmelzer &lt;oe5hpm@oevsv.at&gt;
Cc: Thomas Chou &lt;thomas@wytron.com.tw&gt;
Cc: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Cc: Sam Protsenko &lt;semen.protsenko@linaro.org&gt;
Cc: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Cc: Christophe Ricard &lt;christophe-h.ricard@st.com&gt;
Cc: Anand Moon &lt;linux.amoon@gmail.com&gt;
Cc: Beniamino Galvani &lt;b.galvani@gmail.com&gt;
Cc: Carlo Caione &lt;carlo@endlessm.com&gt;
Cc: huang lin &lt;hl@rock-chips.com&gt;
Cc: Sjoerd Simons &lt;sjoerd.simons@collabora.co.uk&gt;
Cc: Xu Ziyuan &lt;xzy.xu@rock-chips.com&gt;
Cc: "jk.kernel@gmail.com" &lt;jk.kernel@gmail.com&gt;
Cc: "Ariel D'Alessandro" &lt;ariel@vanguardiasur.com.ar&gt;
Cc: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Cc: Samuel Egli &lt;samuel.egli@siemens.com&gt;
Cc: Chin Liang See &lt;clsee@altera.com&gt;
Cc: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
Cc: Hans de Goede &lt;hdegoede@redhat.com&gt;
Cc: Ian Campbell &lt;ijc@hellion.org.uk&gt;
Cc: Siarhei Siamashka &lt;siarhei.siamashka@gmail.com&gt;
Cc: Boris Brezillon &lt;boris.brezillon@free-electrons.com&gt;
Cc: Andre Przywara &lt;andre.przywara@arm.com&gt;
Cc: Bernhard Nortmann &lt;bernhard.nortmann@web.de&gt;
Cc: Wolfgang Denk &lt;wd@denx.de&gt;
Cc: Ben Whitten &lt;ben.whitten@gmail.com&gt;
Cc: Tom Warren &lt;twarren@nvidia.com&gt;
Cc: Alexander Graf &lt;agraf@suse.de&gt;
Cc: Sekhar Nori &lt;nsekhar@ti.com&gt;
Cc: Vitaly Andrianov &lt;vitalya@ti.com&gt;
Cc: "Andrew F. Davis" &lt;afd@ti.com&gt;
Cc: Murali Karicheri &lt;m-karicheri2@ti.com&gt;
Cc: Carlos Hernandez &lt;ceh@ti.com&gt;
Cc: Ladislav Michl &lt;ladis@linux-mips.org&gt;
Cc: Ash Charles &lt;ashcharles@gmail.com&gt;
Cc: Mugunthan V N &lt;mugunthanvnm@ti.com&gt;
Cc: Daniel Allred &lt;d-allred@ti.com&gt;
Cc: Gong Qianyu &lt;Qianyu.Gong@freescale.com&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
Acked-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Acked-by: Chin Liang See &lt;clsee@altera.com&gt;
Tested-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Acked-by: Paul Kocialkowski &lt;contact@paulk.fr&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This series moves the CONFIG_SYS_CACHELINE_SIZE.  First, in nearly all
cases we are mirroring the values used by the Linux Kernel here.  Also,
so long as (and in this case, it is true) we implement flushes in hunks
that are no larger than the smallest implementation (and given that we
mirror the Linux Kernel, again we are fine) it is OK to align higher.
The biggest changes here are that we always use 64 bytes for CPU_V7 even
if for example the underlying core is only 32 bytes (this mirrors
Linux).  Second, we say ARM64 uses 64 bytes not 128 (as found in the
Linux Kernel) as we do not need multi-platform support (to this degree)
and only the Cavium ThunderX 88xx series has a use for such large
alignment.

Cc: Albert Aribaud &lt;albert.u.boot@aribaud.net&gt;
Cc: Marek Vasut &lt;marex@denx.de&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Cc: Prafulla Wadaskar &lt;prafulla@marvell.com&gt;
Cc: Luka Perkov &lt;luka.perkov@sartura.hr&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Cc: Nagendra T S &lt;nagendra@mistralsolutions.com&gt;
Cc: Vaibhav Hiremath &lt;hvaibhav@ti.com&gt;
Acked-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
Cc: Steve Rae &lt;steve.rae@raedomain.com&gt;
Cc: Igor Grinberg &lt;grinberg@compulab.co.il&gt;
Cc: Nikita Kiryanov &lt;nikita@compulab.co.il&gt;
Cc: Stefan Agner &lt;stefan.agner@toradex.com&gt;
Acked-by: Heiko Schocher &lt;hs@denx.de&gt;
Cc: Mateusz Kulikowski &lt;mateusz.kulikowski@gmail.com&gt;
Cc: Peter Griffin &lt;peter.griffin@linaro.org&gt;
Acked-by: Paul Kocialkowski &lt;contact@paulk.fr&gt;
Cc: Anatolij Gustschin &lt;agust@denx.de&gt;
Acked-by: "Pali Rohár" &lt;pali.rohar@gmail.com&gt;
Cc: Adam Ford &lt;aford173@gmail.com&gt;
Cc: Steve Sakoman &lt;sakoman@gmail.com&gt;
Cc: Grazvydas Ignotas &lt;notasas@gmail.com&gt;
Cc: Nishanth Menon &lt;nm@ti.com&gt;
Cc: Stephen Warren &lt;swarren@wwwdotorg.org&gt;
Cc: Robert Baldyga &lt;r.baldyga@samsung.com&gt;
Cc: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
Cc: Thomas Weber &lt;weber@corscience.de&gt;
Cc: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Cc: David Feng &lt;fenghua@phytium.com.cn&gt;
Cc: Alison Wang &lt;b18965@freescale.com&gt;
Cc: Michal Simek &lt;michal.simek@xilinx.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: York Sun &lt;york.sun@nxp.com&gt;
Cc: Shengzhou Liu &lt;Shengzhou.Liu@nxp.com&gt;
Cc: Mingkai Hu &lt;mingkai.hu@nxp.com&gt;
Cc: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
Cc: Aneesh Bansal &lt;aneesh.bansal@freescale.com&gt;
Cc: Saksham Jain &lt;saksham.jain@nxp.com&gt;
Cc: Qianyu Gong &lt;qianyu.gong@nxp.com&gt;
Cc: Wang Dongsheng &lt;dongsheng.wang@nxp.com&gt;
Cc: Alex Porosanu &lt;alexandru.porosanu@freescale.com&gt;
Cc: Hongbo Zhang &lt;hongbo.zhang@nxp.com&gt;
Cc: tang yuantian &lt;Yuantian.Tang@freescale.com&gt;
Cc: Rajesh Bhagat &lt;rajesh.bhagat@nxp.com&gt;
Cc: Josh Wu &lt;josh.wu@atmel.com&gt;
Cc: Bo Shen &lt;voice.shen@atmel.com&gt;
Cc: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
Cc: Hannes Schmelzer &lt;oe5hpm@oevsv.at&gt;
Cc: Thomas Chou &lt;thomas@wytron.com.tw&gt;
Cc: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Cc: Sam Protsenko &lt;semen.protsenko@linaro.org&gt;
Cc: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Cc: Christophe Ricard &lt;christophe-h.ricard@st.com&gt;
Cc: Anand Moon &lt;linux.amoon@gmail.com&gt;
Cc: Beniamino Galvani &lt;b.galvani@gmail.com&gt;
Cc: Carlo Caione &lt;carlo@endlessm.com&gt;
Cc: huang lin &lt;hl@rock-chips.com&gt;
Cc: Sjoerd Simons &lt;sjoerd.simons@collabora.co.uk&gt;
Cc: Xu Ziyuan &lt;xzy.xu@rock-chips.com&gt;
Cc: "jk.kernel@gmail.com" &lt;jk.kernel@gmail.com&gt;
Cc: "Ariel D'Alessandro" &lt;ariel@vanguardiasur.com.ar&gt;
Cc: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Cc: Samuel Egli &lt;samuel.egli@siemens.com&gt;
Cc: Chin Liang See &lt;clsee@altera.com&gt;
Cc: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
Cc: Hans de Goede &lt;hdegoede@redhat.com&gt;
Cc: Ian Campbell &lt;ijc@hellion.org.uk&gt;
Cc: Siarhei Siamashka &lt;siarhei.siamashka@gmail.com&gt;
Cc: Boris Brezillon &lt;boris.brezillon@free-electrons.com&gt;
Cc: Andre Przywara &lt;andre.przywara@arm.com&gt;
Cc: Bernhard Nortmann &lt;bernhard.nortmann@web.de&gt;
Cc: Wolfgang Denk &lt;wd@denx.de&gt;
Cc: Ben Whitten &lt;ben.whitten@gmail.com&gt;
Cc: Tom Warren &lt;twarren@nvidia.com&gt;
Cc: Alexander Graf &lt;agraf@suse.de&gt;
Cc: Sekhar Nori &lt;nsekhar@ti.com&gt;
Cc: Vitaly Andrianov &lt;vitalya@ti.com&gt;
Cc: "Andrew F. Davis" &lt;afd@ti.com&gt;
Cc: Murali Karicheri &lt;m-karicheri2@ti.com&gt;
Cc: Carlos Hernandez &lt;ceh@ti.com&gt;
Cc: Ladislav Michl &lt;ladis@linux-mips.org&gt;
Cc: Ash Charles &lt;ashcharles@gmail.com&gt;
Cc: Mugunthan V N &lt;mugunthanvnm@ti.com&gt;
Cc: Daniel Allred &lt;d-allred@ti.com&gt;
Cc: Gong Qianyu &lt;Qianyu.Gong@freescale.com&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
Acked-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Acked-by: Chin Liang See &lt;clsee@altera.com&gt;
Tested-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Acked-by: Paul Kocialkowski &lt;contact@paulk.fr&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: Show cache warnings in U-Boot proper only</title>
<updated>2016-07-14T22:33:11+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-06-20T01:43:05+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=bcc53bf095893fbdae531a9a7b5d4ef4a125a7fc'/>
<id>bcc53bf095893fbdae531a9a7b5d4ef4a125a7fc</id>
<content type='text'>
Avoid bloating the SPL image size.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Avoid bloating the SPL image size.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: Move check_cache_range() into a common place</title>
<updated>2016-07-14T22:33:09+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-06-20T01:43:01+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=397b5697ad242408979a00dda14138aa1439f52b'/>
<id>397b5697ad242408979a00dda14138aa1439f52b</id>
<content type='text'>
This code is common, so move it into a common file.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This code is common, so move it into a common file.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Marek Vasut &lt;marex@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: support Thumb-1 with CONFIG_SYS_THUMB_BUILD</title>
<updated>2015-11-10T14:03:48+00:00</updated>
<author>
<name>Albert ARIBAUD</name>
<email>albert.u.boot@aribaud.net</email>
</author>
<published>2015-10-23T16:06:40+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=62e92077a8936e60087d55683538ee386cc673aa'/>
<id>62e92077a8936e60087d55683538ee386cc673aa</id>
<content type='text'>
When building a Thumb-1-only target with CONFIG_SYS_THUMB_BUILD,
some files fail to build, most of the time because they include
mcr instructions, which only exist for Thumb-2.

This patch introduces a Kconfig option CONFIG_THUMB2 and uses
it to select between Thumb-2 and ARM mode for the aforementioned
files.

Signed-off-by: Albert ARIBAUD &lt;albert.u.boot@aribaud.net&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
When building a Thumb-1-only target with CONFIG_SYS_THUMB_BUILD,
some files fail to build, most of the time because they include
mcr instructions, which only exist for Thumb-2.

This patch introduces a Kconfig option CONFIG_THUMB2 and uses
it to select between Thumb-2 and ARM mode for the aforementioned
files.

Signed-off-by: Albert ARIBAUD &lt;albert.u.boot@aribaud.net&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: cache: implement a default weak flush_cache() function</title>
<updated>2015-08-13T00:47:48+00:00</updated>
<author>
<name>Wu, Josh</name>
<email>Josh.wu@atmel.com</email>
</author>
<published>2015-07-27T03:40:17+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=633b6ccedf9d536fd93299b2207a5227dedd987c'/>
<id>633b6ccedf9d536fd93299b2207a5227dedd987c</id>
<content type='text'>
Current many cpu use the same flush_cache() function, which just call
the flush_dcache_range().
So implement a weak flush_cache() for all the cpus to use.

In original weak flush_cache() in arch/arm/lib/cache.c, there has some
code for ARM1136 &amp; ARM926ejs. But in the arch/arm/cpu/arm1136/cpu.c and
arch/arm/cpu/arm926ejs/cache.c, there implements a real flush_cache()
function as well. That means the original code for ARM1136 &amp; ARM926ejs
in weak flush_cache() of arch/arm/lib/cache.c is totally useless.

So in this patch remove such code in flush_cache() and only call
flush_dcache_range().

Signed-off-by: Josh Wu &lt;josh.wu@atmel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Current many cpu use the same flush_cache() function, which just call
the flush_dcache_range().
So implement a weak flush_cache() for all the cpus to use.

In original weak flush_cache() in arch/arm/lib/cache.c, there has some
code for ARM1136 &amp; ARM926ejs. But in the arch/arm/cpu/arm1136/cpu.c and
arch/arm/cpu/arm926ejs/cache.c, there implements a real flush_cache()
function as well. That means the original code for ARM1136 &amp; ARM926ejs
in weak flush_cache() of arch/arm/lib/cache.c is totally useless.

So in this patch remove such code in flush_cache() and only call
flush_dcache_range().

Signed-off-by: Josh Wu &lt;josh.wu@atmel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: cache: add an empty stub function for invalidate/flush dcache</title>
<updated>2015-08-13T00:47:47+00:00</updated>
<author>
<name>Wu, Josh</name>
<email>Josh.wu@atmel.com</email>
</author>
<published>2015-07-27T03:40:16+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=387871a10edc777a5d94bfdbd6b86e493991826e'/>
<id>387871a10edc777a5d94bfdbd6b86e493991826e</id>
<content type='text'>
Since some driver like ohci, lcd used dcache functions. But some ARM
cpu don't implement the invalidate_dcache_range()/flush_dcache_range()
functions.

To avoid compiling errors this patch adds an weak empty stub function
for all ARM cpu in arch/arm/lib/cache.c.
And ARM cpu still can implemnt its own cache functions on the cpu folder.

Signed-off-by: Josh Wu &lt;josh.wu@atmel.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Since some driver like ohci, lcd used dcache functions. But some ARM
cpu don't implement the invalidate_dcache_range()/flush_dcache_range()
functions.

To avoid compiling errors this patch adds an weak empty stub function
for all ARM cpu in arch/arm/lib/cache.c.
And ARM cpu still can implemnt its own cache functions on the cpu folder.

Signed-off-by: Josh Wu &lt;josh.wu@atmel.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm, arm926ejs: make thumb mode compileable</title>
<updated>2015-01-19T11:49:26+00:00</updated>
<author>
<name>Heiko Schocher</name>
<email>hs@denx.de</email>
</author>
<published>2014-11-18T08:41:56+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=99197a9e316cbedd315135fcfd7673221a746df7'/>
<id>99197a9e316cbedd315135fcfd7673221a746df7</id>
<content type='text'>
in thumb mode compiler says for example for arch/arm/lib/cache-cp15.c
when enabling CONFIG_SYS_THUMB_BUILD:

{standard input}: Assembler messages:
{standard input}:373: Error: selected processor does not support Thumb mode `mrc p15,0,r4,c1,c0,0'
{standard input}:416: Error: selected processor does not support Thumb mode `mcr p15,0,r3,c2,c0,0'

so, if caches are disabled, do not use this command on arm926ejs.
used on at91 in SPL, to reduce size of SPL.

Signed-off-by: Heiko Schocher &lt;hs@denx.de&gt;
</content>
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<pre>
in thumb mode compiler says for example for arch/arm/lib/cache-cp15.c
when enabling CONFIG_SYS_THUMB_BUILD:

{standard input}: Assembler messages:
{standard input}:373: Error: selected processor does not support Thumb mode `mrc p15,0,r4,c1,c0,0'
{standard input}:416: Error: selected processor does not support Thumb mode `mcr p15,0,r3,c2,c0,0'

so, if caches are disabled, do not use this command on arm926ejs.
used on at91 in SPL, to reduce size of SPL.

Signed-off-by: Heiko Schocher &lt;hs@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: Implement non-cached memory support</title>
<updated>2014-12-18T20:19:21+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-12-10T05:25:22+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1dfdd9ba4e699562a3b282f4fb5efe4c80e6e8c7'/>
<id>1dfdd9ba4e699562a3b282f4fb5efe4c80e6e8c7</id>
<content type='text'>
Implement an API that can be used by drivers to allocate memory from a
pool that is mapped uncached. This is useful if drivers would otherwise
need to do extensive cache maintenance (or explicitly maintaining the
cache isn't safe).

The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting.
Boards can set this to the size to be used for the non-cached area. The
area will typically be right below the malloc() area, but architectures
should take care of aligning the beginning and end of the area to honor
any mapping restrictions. Architectures must also ensure that mappings
established for this area do not overlap with the malloc() area (which
should remain cached for improved performance).

While the API is currently only implemented for ARM v7, it should be
generic enough to allow other architectures to implement it as well.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
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<pre>
Implement an API that can be used by drivers to allocate memory from a
pool that is mapped uncached. This is useful if drivers would otherwise
need to do extensive cache maintenance (or explicitly maintaining the
cache isn't safe).

The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting.
Boards can set this to the size to be used for the non-cached area. The
area will typically be right below the malloc() area, but architectures
should take care of aligning the beginning and end of the area to honor
any mapping restrictions. Architectures must also ensure that mappings
established for this area do not overlap with the malloc() area (which
should remain cached for improved performance).

While the API is currently only implemented for ARM v7, it should be
generic enough to allow other architectures to implement it as well.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: remove CONFIG_ARM1136 defines</title>
<updated>2014-11-20T16:28:25+00:00</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2014-11-06T05:59:37+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3fd968e9314942f2840f8f9fda98079cc0d82288'/>
<id>3fd968e9314942f2840f8f9fda98079cc0d82288</id>
<content type='text'>
CONFIG_CPU_ARM1136 was introduced into Kconfig by commit 2e07c249a67e
(kconfig: arm: introduce symbol for ARM CPUs).

This commit removes all the defines of CONFIG_ARM1136 and replaces
the only reference in arch/arm/lib/cache.c with CONFIG_CPU_ARM1136.

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
</content>
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<pre>
CONFIG_CPU_ARM1136 was introduced into Kconfig by commit 2e07c249a67e
(kconfig: arm: introduce symbol for ARM CPUs).

This commit removes all the defines of CONFIG_ARM1136 and replaces
the only reference in arch/arm/lib/cache.c with CONFIG_CPU_ARM1136.

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: remove CONFIG_ARM926EJS defines</title>
<updated>2014-11-20T16:28:25+00:00</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2014-11-06T05:59:36+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5d7b131d41d8a8fb50edf27d945703e757ed8357'/>
<id>5d7b131d41d8a8fb50edf27d945703e757ed8357</id>
<content type='text'>
CONFIG_CPU_ARM926EJS was introduced into Kconfig by commit 2e07c249a67e
(kconfig: arm: introduce symbol for ARM CPUs).

This commit removes all the defines of CONFIG_ARM926EJS and replaces
the only reference in arch/arm/lib/cache.c with CONFIG_CPU_ARM926EJS.

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
CONFIG_CPU_ARM926EJS was introduced into Kconfig by commit 2e07c249a67e
(kconfig: arm: introduce symbol for ARM CPUs).

This commit removes all the defines of CONFIG_ARM926EJS and replaces
the only reference in arch/arm/lib/cache.c with CONFIG_CPU_ARM926EJS.

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
