u-boot.git/arch/arm/lib/cache.c, branch v2018.09

SPDX: Convert all of our single license tags to Linux Kernel style

2018-05-07T13:34:12+00:00

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini

arm: Migrate SYS_THUMB_BUILD to Kconfig, introduce SPL_SYS_THUMB_BUILD

2017-03-19T00:28:01+00:00

Today, we have cases where we wish to build all of U-Boot in Thumb2 mode for
various reasons.  We also have cases where we only build SPL in Thumb2 mode due
to size constraints and wish to build the rest of the system in ARM mode.  So
in this migration we introduce a new symbol as well, SPL_SYS_THUMB_BUILD to
control if we build everything or just SPL (or in theory, just U-Boot) in
Thumb2 mode.

Signed-off-by: Tom Rini 
Acked-by: Siarhei Siamashka

ARM: Move SYS_CACHELINE_SIZE over to Kconfig

2016-08-26T21:04:46+00:00

This series moves the CONFIG_SYS_CACHELINE_SIZE.  First, in nearly all
cases we are mirroring the values used by the Linux Kernel here.  Also,
so long as (and in this case, it is true) we implement flushes in hunks
that are no larger than the smallest implementation (and given that we
mirror the Linux Kernel, again we are fine) it is OK to align higher.
The biggest changes here are that we always use 64 bytes for CPU_V7 even
if for example the underlying core is only 32 bytes (this mirrors
Linux).  Second, we say ARM64 uses 64 bytes not 128 (as found in the
Linux Kernel) as we do not need multi-platform support (to this degree)
and only the Cavium ThunderX 88xx series has a use for such large
alignment.

Cc: Albert Aribaud 
Cc: Marek Vasut 
Cc: Stefano Babic 
Cc: Prafulla Wadaskar 
Cc: Luka Perkov 
Cc: Stefan Roese 
Cc: Nagendra T S 
Cc: Vaibhav Hiremath 
Acked-by: Lokesh Vutla 
Cc: Steve Rae 
Cc: Igor Grinberg 
Cc: Nikita Kiryanov 
Cc: Stefan Agner 
Acked-by: Heiko Schocher 
Cc: Mateusz Kulikowski 
Cc: Peter Griffin 
Acked-by: Paul Kocialkowski 
Cc: Anatolij Gustschin 
Acked-by: "Pali Rohár" 
Cc: Adam Ford 
Cc: Steve Sakoman 
Cc: Grazvydas Ignotas 
Cc: Nishanth Menon 
Cc: Stephen Warren 
Cc: Robert Baldyga 
Cc: Minkyu Kang 
Cc: Thomas Weber 
Cc: Masahiro Yamada 
Cc: David Feng 
Cc: Alison Wang 
Cc: Michal Simek 
Cc: Simon Glass 
Cc: York Sun 
Cc: Shengzhou Liu 
Cc: Mingkai Hu 
Cc: Prabhakar Kushwaha 
Cc: Aneesh Bansal 
Cc: Saksham Jain 
Cc: Qianyu Gong 
Cc: Wang Dongsheng 
Cc: Alex Porosanu 
Cc: Hongbo Zhang 
Cc: tang yuantian 
Cc: Rajesh Bhagat 
Cc: Josh Wu 
Cc: Bo Shen 
Cc: Viresh Kumar 
Cc: Hannes Schmelzer 
Cc: Thomas Chou 
Cc: Joe Hershberger 
Cc: Sam Protsenko 
Cc: Bin Meng 
Cc: Christophe Ricard 
Cc: Anand Moon 
Cc: Beniamino Galvani 
Cc: Carlo Caione 
Cc: huang lin 
Cc: Sjoerd Simons 
Cc: Xu Ziyuan 
Cc: "jk.kernel@gmail.com" 
Cc: "Ariel D'Alessandro" 
Cc: Kever Yang 
Cc: Samuel Egli 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Hans de Goede 
Cc: Ian Campbell 
Cc: Siarhei Siamashka 
Cc: Boris Brezillon 
Cc: Andre Przywara 
Cc: Bernhard Nortmann 
Cc: Wolfgang Denk 
Cc: Ben Whitten 
Cc: Tom Warren 
Cc: Alexander Graf 
Cc: Sekhar Nori 
Cc: Vitaly Andrianov 
Cc: "Andrew F. Davis" 
Cc: Murali Karicheri 
Cc: Carlos Hernandez 
Cc: Ladislav Michl 
Cc: Ash Charles 
Cc: Mugunthan V N 
Cc: Daniel Allred 
Cc: Gong Qianyu 
Signed-off-by: Tom Rini 
Acked-by: Masahiro Yamada 
Acked-by: Chin Liang See 
Tested-by: Stephen Warren 
Acked-by: Paul Kocialkowski

arm: Show cache warnings in U-Boot proper only

2016-07-14T22:33:11+00:00

Avoid bloating the SPL image size.

Signed-off-by: Simon Glass

arm: Move check_cache_range() into a common place

2016-07-14T22:33:09+00:00

This code is common, so move it into a common file.

Signed-off-by: Simon Glass 
Reviewed-by: Marek Vasut

arm: support Thumb-1 with CONFIG_SYS_THUMB_BUILD

2015-11-10T14:03:48+00:00

When building a Thumb-1-only target with CONFIG_SYS_THUMB_BUILD,
some files fail to build, most of the time because they include
mcr instructions, which only exist for Thumb-2.

This patch introduces a Kconfig option CONFIG_THUMB2 and uses
it to select between Thumb-2 and ARM mode for the aforementioned
files.

Signed-off-by: Albert ARIBAUD

ARM: cache: implement a default weak flush_cache() function

2015-08-13T00:47:48+00:00

Current many cpu use the same flush_cache() function, which just call
the flush_dcache_range().
So implement a weak flush_cache() for all the cpus to use.

In original weak flush_cache() in arch/arm/lib/cache.c, there has some
code for ARM1136 & ARM926ejs. But in the arch/arm/cpu/arm1136/cpu.c and
arch/arm/cpu/arm926ejs/cache.c, there implements a real flush_cache()
function as well. That means the original code for ARM1136 & ARM926ejs
in weak flush_cache() of arch/arm/lib/cache.c is totally useless.

So in this patch remove such code in flush_cache() and only call
flush_dcache_range().

Signed-off-by: Josh Wu

ARM: cache: add an empty stub function for invalidate/flush dcache

2015-08-13T00:47:47+00:00

Since some driver like ohci, lcd used dcache functions. But some ARM
cpu don't implement the invalidate_dcache_range()/flush_dcache_range()
functions.

To avoid compiling errors this patch adds an weak empty stub function
for all ARM cpu in arch/arm/lib/cache.c.
And ARM cpu still can implemnt its own cache functions on the cpu folder.

Signed-off-by: Josh Wu 
Reviewed-by: York Sun

arm, arm926ejs: make thumb mode compileable

2015-01-19T11:49:26+00:00

in thumb mode compiler says for example for arch/arm/lib/cache-cp15.c
when enabling CONFIG_SYS_THUMB_BUILD:

{standard input}: Assembler messages:
{standard input}:373: Error: selected processor does not support Thumb mode `mrc p15,0,r4,c1,c0,0'
{standard input}:416: Error: selected processor does not support Thumb mode `mcr p15,0,r3,c2,c0,0'

so, if caches are disabled, do not use this command on arm926ejs.
used on at91 in SPL, to reduce size of SPL.

Signed-off-by: Heiko Schocher

ARM: Implement non-cached memory support

2014-12-18T20:19:21+00:00

Implement an API that can be used by drivers to allocate memory from a
pool that is mapped uncached. This is useful if drivers would otherwise
need to do extensive cache maintenance (or explicitly maintaining the
cache isn't safe).

The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting.
Boards can set this to the size to be used for the non-cached area. The
area will typically be right below the malloc() area, but architectures
should take care of aligning the beginning and end of the area to honor
any mapping restrictions. Architectures must also ensure that mappings
established for this area do not overlap with the malloc() area (which
should remain cached for improved performance).

While the API is currently only implemented for ARM v7, it should be
generic enough to allow other architectures to implement it as well.

Signed-off-by: Thierry Reding 
Signed-off-by: Simon Glass 
Signed-off-by: Tom Warren