u-boot.git/arch/arm/lib/cache.c, branch v2020.04

common: Move ARM cache operations out of common.h

2019-12-02T23:24:58Z

These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass Reviewed-by: Daniel Schwierzeck Reviewed-by: Tom Rini

board_f: fix noncached reservation calculation

2019-08-30T18:17:11Z

The current code in reserve_noncached() has two issues: 1) The first update of gd->start_addr_sp always rounds down to a section start. However, the equivalent calculation in cache.c:noncached_init() always first rounds up to a section start, then subtracts a section size. These two calculations differ if the initial value is already rounded to section alignment. 2) The second update of gd->start_addr_sp subtracts exactly CONFIG_SYS_NONCACHED_MEMORY, whereas the equivalent calculation in cache.c:noncached_init() rounds the noncached size up to section alignment before subtracting it. The two calculations differ if the noncached region size is not a multiple of the MMU section size. In practice, one/both of those issues causes a practical problem on Jetson TX1; U-Boot triggers a synchronous abort during initialization, likely due to overlapping use of some memory region. This change fixes both these issues by duplicating the exact calculations from noncached_init() into reserve_noncached(). However, this fix assumes that gd->start_addr_sp on entry to reserve_noncached() exactly matches mem_malloc_start on entry to noncached_init(). I haven't traced the code to see whether it absolutely guarantees this in all (or indeed any!) cases. Consequently, I added some comments in the hope that this condition will continue to be true. Fixes: 5f7adb5b1c02 ("board_f: reserve noncached space below malloc area") Cc: Vikas Manocha Signed-off-by: Stephen Warren

CONFIG_SPL_SYS_[DI]CACHE_OFF: add

2019-05-18T12:15:35Z

While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin Signed-off-by: Trevor Woerner [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini

SPDX: Convert all of our single license tags to Linux Kernel style

2018-05-07T13:34:12Z

When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini

arm: Migrate SYS_THUMB_BUILD to Kconfig, introduce SPL_SYS_THUMB_BUILD

2017-03-19T00:28:01Z

Today, we have cases where we wish to build all of U-Boot in Thumb2 mode for various reasons. We also have cases where we only build SPL in Thumb2 mode due to size constraints and wish to build the rest of the system in ARM mode. So in this migration we introduce a new symbol as well, SPL_SYS_THUMB_BUILD to control if we build everything or just SPL (or in theory, just U-Boot) in Thumb2 mode. Signed-off-by: Tom Rini Acked-by: Siarhei Siamashka

ARM: Move SYS_CACHELINE_SIZE over to Kconfig

2016-08-26T21:04:46Z

This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all cases we are mirroring the values used by the Linux Kernel here. Also, so long as (and in this case, it is true) we implement flushes in hunks that are no larger than the smallest implementation (and given that we mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even if for example the underlying core is only 32 bytes (this mirrors Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the Linux Kernel) as we do not need multi-platform support (to this degree) and only the Cavium ThunderX 88xx series has a use for such large alignment. Cc: Albert Aribaud Cc: Marek Vasut Cc: Stefano Babic Cc: Prafulla Wadaskar Cc: Luka Perkov Cc: Stefan Roese Cc: Nagendra T S Cc: Vaibhav Hiremath Acked-by: Lokesh Vutla Cc: Steve Rae Cc: Igor Grinberg Cc: Nikita Kiryanov Cc: Stefan Agner Acked-by: Heiko Schocher Cc: Mateusz Kulikowski Cc: Peter Griffin Acked-by: Paul Kocialkowski Cc: Anatolij Gustschin Acked-by: "Pali Rohár" Cc: Adam Ford Cc: Steve Sakoman Cc: Grazvydas Ignotas Cc: Nishanth Menon Cc: Stephen Warren Cc: Robert Baldyga Cc: Minkyu Kang Cc: Thomas Weber Cc: Masahiro Yamada Cc: David Feng Cc: Alison Wang Cc: Michal Simek Cc: Simon Glass Cc: York Sun Cc: Shengzhou Liu Cc: Mingkai Hu Cc: Prabhakar Kushwaha Cc: Aneesh Bansal Cc: Saksham Jain Cc: Qianyu Gong Cc: Wang Dongsheng Cc: Alex Porosanu Cc: Hongbo Zhang Cc: tang yuantian Cc: Rajesh Bhagat Cc: Josh Wu Cc: Bo Shen Cc: Viresh Kumar Cc: Hannes Schmelzer Cc: Thomas Chou Cc: Joe Hershberger Cc: Sam Protsenko Cc: Bin Meng Cc: Christophe Ricard Cc: Anand Moon Cc: Beniamino Galvani Cc: Carlo Caione Cc: huang lin Cc: Sjoerd Simons Cc: Xu Ziyuan Cc: "jk.kernel@gmail.com" Cc: "Ariel D'Alessandro" Cc: Kever Yang Cc: Samuel Egli Cc: Chin Liang See Cc: Dinh Nguyen Cc: Hans de Goede Cc: Ian Campbell Cc: Siarhei Siamashka Cc: Boris Brezillon Cc: Andre Przywara Cc: Bernhard Nortmann Cc: Wolfgang Denk Cc: Ben Whitten Cc: Tom Warren Cc: Alexander Graf Cc: Sekhar Nori Cc: Vitaly Andrianov Cc: "Andrew F. Davis" Cc: Murali Karicheri Cc: Carlos Hernandez Cc: Ladislav Michl Cc: Ash Charles Cc: Mugunthan V N Cc: Daniel Allred Cc: Gong Qianyu Signed-off-by: Tom Rini Acked-by: Masahiro Yamada Acked-by: Chin Liang See Tested-by: Stephen Warren Acked-by: Paul Kocialkowski

arm: Show cache warnings in U-Boot proper only

2016-07-14T22:33:11Z

Avoid bloating the SPL image size. Signed-off-by: Simon Glass

arm: Move check_cache_range() into a common place

2016-07-14T22:33:09Z

This code is common, so move it into a common file. Signed-off-by: Simon Glass Reviewed-by: Marek Vasut

arm: support Thumb-1 with CONFIG_SYS_THUMB_BUILD

2015-11-10T14:03:48Z

When building a Thumb-1-only target with CONFIG_SYS_THUMB_BUILD, some files fail to build, most of the time because they include mcr instructions, which only exist for Thumb-2. This patch introduces a Kconfig option CONFIG_THUMB2 and uses it to select between Thumb-2 and ARM mode for the aforementioned files. Signed-off-by: Albert ARIBAUD

ARM: cache: implement a default weak flush_cache() function

2015-08-13T00:47:48Z

Current many cpu use the same flush_cache() function, which just call the flush_dcache_range(). So implement a weak flush_cache() for all the cpus to use. In original weak flush_cache() in arch/arm/lib/cache.c, there has some code for ARM1136 & ARM926ejs. But in the arch/arm/cpu/arm1136/cpu.c and arch/arm/cpu/arm926ejs/cache.c, there implements a real flush_cache() function as well. That means the original code for ARM1136 & ARM926ejs in weak flush_cache() of arch/arm/lib/cache.c is totally useless. So in this patch remove such code in flush_cache() and only call flush_dcache_range(). Signed-off-by: Josh Wu