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<title>u-boot.git/arch/arm/lib/cache.c, branch v2020.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/lib/cache.c?h=v2020.07</id>
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<updated>2020-05-19T01:19:18Z</updated>
<entry>
<title>common: Drop log.h from common header</title>
<updated>2020-05-19T01:19:18Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-05-10T17:40:05Z</published>
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<id>urn:sha1:f7ae49fc4f363a803dab3be078e93ead8e75a8e9</id>
<content type='text'>
Move this header out of the common header.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>common: Drop net.h from common header</title>
<updated>2020-05-18T21:33:31Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-05-10T17:39:56Z</published>
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<id>urn:sha1:90526e9fbac47af16d70f323feae45d8d1b0f9b7</id>
<content type='text'>
Move this header out of the common header. Network support is used in
quite a few places but it still does not warrant blanket inclusion.

Note that this net.h header itself has quite a lot in it. It could be
split into the driver-mode support, functions, structures, checksumming,
etc.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>cmd: cache: Fix non-cached memory cachability</title>
<updated>2020-05-07T13:01:42Z</updated>
<author>
<name>Patrice Chotard</name>
<email>patrice.chotard@st.com</email>
</author>
<published>2020-04-28T09:38:03Z</published>
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<id>urn:sha1:c2a2123e33371b2dc3406789764996d4fa73aac3</id>
<content type='text'>
If dcache is switched OFF to ON state and if non-cached memory is
used, this non-cached memory must be re-declared as uncached to mmu
each time dcache is set ON.

Introduce noncached_set_region() to set this non-cached region's mmu
settings. Let architecture override it by defining it as a weak
function.

For ARM architecture, noncached_set_region() defines all noncached
region as non-cacheable.

Issue found on STM32MP1 platform using dwc_eth_qos ethernet driver,
when going from dcache OFF to dcache ON state, ethernet driver issued
TX timeout errors when performing dhcp or ping.

It can be reproduced with the following sequence:

dhcp
while true ; do
  ping 192.168.1.300 ;
  dcache off ;
  ping 192.168.1.300 ;
  dcache on ;
done

Signed-off-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
Cc: Marek Vasut &lt;marex@denx.de&gt;
Cc: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Cc: Ramon Fried &lt;rfried.dev@gmail.com&gt;
Cc: Stephen Warren &lt;swarren@nvidia.com&gt;
Reviewed-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
</entry>
<entry>
<title>common/board_f: Make reserve_mmu generic</title>
<updated>2020-04-24T19:17:14Z</updated>
<author>
<name>Ovidiu Panait</name>
<email>ovpanait@gmail.com</email>
</author>
<published>2020-03-29T17:57:41Z</published>
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<id>urn:sha1:79926e4f2f3cf84c65188c59ea1e93d6b221d36b</id>
<content type='text'>
Introduce arch_reserve_mmu to allow for architecture-specific reserve_mmu
routines. Also, define a weak nop stub for it.

Signed-off-by: Ovidiu Panait &lt;ovpanait@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>arm: asm/cache.c: Introduce arm_reserve_mmu</title>
<updated>2020-04-24T19:17:14Z</updated>
<author>
<name>Ovidiu Panait</name>
<email>ovpanait@gmail.com</email>
</author>
<published>2020-03-29T17:57:40Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6184858b859f6fcea4b23f76cfb7988882a3c8a7'/>
<id>urn:sha1:6184858b859f6fcea4b23f76cfb7988882a3c8a7</id>
<content type='text'>
As a preparation for turning reserve_mmu into an arch-specific variant,
introduce arm_reserve_mmu on ARM. It implements the default routine for
reserving memory for MMU TLB and needs to be weakly defined in order to allow
for machines to override it.

Without this decoupling, after introducing arch_reserve_mmu, there would be two
weak definitions for it, one in common/board_f.c and one in
arch/arm/lib/cache.c.

Signed-off-by: Ovidiu Panait &lt;ovpanait@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>common/board_f: Move arm-specific reserve_mmu to arch/arm/lib/cache.c</title>
<updated>2020-04-24T19:17:14Z</updated>
<author>
<name>Ovidiu Panait</name>
<email>ovpanait@gmail.com</email>
</author>
<published>2020-03-29T17:57:39Z</published>
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<id>urn:sha1:586b15bce82a2161dbe71991c14c8c36f5683033</id>
<content type='text'>
Move the ARM-specific reserve_mmu definition from common/board_f.c
to arch/arm/lib/cache.c.

Signed-off-by: Ovidiu Panait &lt;ovpanait@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>common: Move ARM cache operations out of common.h</title>
<updated>2019-12-02T23:24:58Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-11-14T19:57:39Z</published>
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<id>urn:sha1:1eb69ae498567bb0b62ee554647204e8245cdacc</id>
<content type='text'>
These functions are CPU-related and do not use driver model. Move them to
cpu_func.h

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>board_f: fix noncached reservation calculation</title>
<updated>2019-08-30T18:17:11Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2019-08-27T17:54:31Z</published>
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<id>urn:sha1:5e0404ff85fca50b5ac41bf08bbe46e6de4903e7</id>
<content type='text'>
The current code in reserve_noncached() has two issues:

1) The first update of gd-&gt;start_addr_sp always rounds down to a section
start. However, the equivalent calculation in cache.c:noncached_init()
always first rounds up to a section start, then subtracts a section size.
These two calculations differ if the initial value is already rounded to
section alignment.

2) The second update of gd-&gt;start_addr_sp subtracts exactly
CONFIG_SYS_NONCACHED_MEMORY, whereas the equivalent calculation in
cache.c:noncached_init() rounds the noncached size up to section
alignment before subtracting it. The two calculations differ if the
noncached region size is not a multiple of the MMU section size.

In practice, one/both of those issues causes a practical problem on
Jetson TX1; U-Boot triggers a synchronous abort during initialization,
likely due to overlapping use of some memory region.

This change fixes both these issues by duplicating the exact calculations
from noncached_init() into reserve_noncached().

However, this fix assumes that gd-&gt;start_addr_sp on entry to
reserve_noncached() exactly matches mem_malloc_start on entry to
noncached_init(). I haven't traced the code to see whether it absolutely
guarantees this in all (or indeed any!) cases. Consequently, I added some
comments in the hope that this condition will continue to be true.

Fixes: 5f7adb5b1c02 ("board_f: reserve noncached space below malloc area")
Cc: Vikas Manocha &lt;vikas.manocha@st.com&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>CONFIG_SPL_SYS_[DI]CACHE_OFF: add</title>
<updated>2019-05-18T12:15:35Z</updated>
<author>
<name>Trevor Woerner</name>
<email>trevor@toganlabs.com</email>
</author>
<published>2019-05-03T13:41:00Z</published>
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<id>urn:sha1:1001502545ff0125c39232cf0e7f26d9213ab55f</id>
<content type='text'>
While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances
where these configuration items are conditional on SPL. This commit adds SPL
variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates
the configurations as required.

Acked-by: Alexey Brodkin &lt;abrodkin@synopsys.com&gt;
Signed-off-by: Trevor Woerner &lt;trevor@toganlabs.com&gt;
[trini: Make the default depend on the setting for full U-Boot, update
more zynq hardware]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>SPDX: Convert all of our single license tags to Linux Kernel style</title>
<updated>2018-05-07T13:34:12Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-05-06T21:58:06Z</published>
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<id>urn:sha1:83d290c56fab2d38cd1ab4c4cc7099559c1d5046</id>
<content type='text'>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
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