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<title>u-boot.git/arch/arm/lib, branch v2015.10</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/lib?h=v2015.10</id>
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<updated>2015-10-15T12:47:03Z</updated>
<entry>
<title>armv8/gic: Fix GIC v2 initialization</title>
<updated>2015-10-15T12:47:03Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-08-20T09:52:15Z</published>
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<id>urn:sha1:b1964c72bdb9ca44de3a56d40927409b8cab2a76</id>
<content type='text'>
Initialize all GICD_IGROUPRn registers and set up GICC_CTLR to enable
interrupts to the primary CPU. This fixes issues seen after booting a
Linux kernel from U-Boot.

Suggested-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Suggested-by: Mark Rutland &lt;mark.rutland@arm.com&gt;
Cc: Albert Aribaud &lt;albert.u.boot@aribaud.net&gt;
Cc: Mark Rutland &lt;mark.rutland@arm.com&gt;
Cc: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>Merge remote-tracking branch 'u-boot/master'</title>
<updated>2015-10-14T08:46:36Z</updated>
<author>
<name>Albert ARIBAUD</name>
<email>albert.u.boot@aribaud.net</email>
</author>
<published>2015-10-14T08:46:36Z</published>
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<id>urn:sha1:13a3972585af60ec367d209cedbd3601e0c77467</id>
<content type='text'>
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</entry>
<entry>
<title>arm: Drop old non-generic-board code</title>
<updated>2015-09-28T14:48:24Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-09-12T17:50:10Z</published>
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<id>urn:sha1:1090a56c87121e740ba3fcac89739f7bd6c9ac66</id>
<content type='text'>
This code is no-longer used. Drop it.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Andreas Bießmann &lt;andreas.devel@gmail.com&gt;
</content>
</entry>
<entry>
<title>arm: Correct comments in crt0.S for the recent SPL improvements</title>
<updated>2015-09-12T07:00:35Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-08-01T14:55:46Z</published>
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<id>urn:sha1:ed64190f67a28e9830371d424998b8aa924be9f3</id>
<content type='text'>
The current comments need a bit of tweaking since we now support stack
and global_data relocation in SPL. Also add a reference to the README.

For AArch64 this is not implemented, so leave a TODO for this.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reported-by: Tim Harvey &lt;tharvey@gateworks.com&gt;
</content>
</entry>
<entry>
<title>Merge git://git.denx.de/u-boot-rockchip</title>
<updated>2015-09-03T18:57:09Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2015-09-03T18:57:09Z</published>
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<id>urn:sha1:c9feb427aba860ebc79f9851a1bb49cc456a2d48</id>
<content type='text'>
</content>
</entry>
<entry>
<title>arm: reset: Avoid a build error when the reset uclass is enabled</title>
<updated>2015-09-03T03:28:23Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-08-30T22:55:18Z</published>
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<id>urn:sha1:c6aabe9289e4f3a3b9066cd494c413302dfa970a</id>
<content type='text'>
There can be only one do_reset(). When CONFIG_RESET is enabled this is
provided by the reset uclass, and ARM's version should be disabled.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>armv8: Add framework for CCN-504 interconnect configuration</title>
<updated>2015-09-02T02:37:49Z</updated>
<author>
<name>Bhupesh Sharma</name>
<email>bhupesh.sharma@freescale.com</email>
</author>
<published>2015-07-01T04:28:03Z</published>
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<id>urn:sha1:3ffa95c283aa45e97d35c033577ab0b67628f426</id>
<content type='text'>
This patch adds a minimal framework for Dickens CCN-504
interconnect configuration - mainly related to adding Clusters/cores
to snoop/DVM domain and setting QoS of the RN-I ports.

LS2085A platform makes use of these configurations to support
better network data performance and to boot a SMP Linux.

Signed-off-by: Bhupesh Sharma &lt;bhupesh.sharma@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>ARM: SPL: Use CONFIG_SPL_DM not CONFIG_DM</title>
<updated>2015-08-13T00:48:07Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2015-07-31T23:55:10Z</published>
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<id>urn:sha1:b5d92ba1ad97c06985ebc689e1ac1462a146832d</id>
<content type='text'>
We now have the CONFIG_SPL_DM for code within SPL to toggle caring about
DM or not.  Without this change platforms that do enable CONFIG_DM but
not CONFIG_SPL_DM may be broken (such as OMAP5).

Cc: Albert Aribaud &lt;albert.u.boot@aribaud.net&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>ARM: cache: implement a default weak flush_cache() function</title>
<updated>2015-08-13T00:47:48Z</updated>
<author>
<name>Wu, Josh</name>
<email>Josh.wu@atmel.com</email>
</author>
<published>2015-07-27T03:40:17Z</published>
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<id>urn:sha1:633b6ccedf9d536fd93299b2207a5227dedd987c</id>
<content type='text'>
Current many cpu use the same flush_cache() function, which just call
the flush_dcache_range().
So implement a weak flush_cache() for all the cpus to use.

In original weak flush_cache() in arch/arm/lib/cache.c, there has some
code for ARM1136 &amp; ARM926ejs. But in the arch/arm/cpu/arm1136/cpu.c and
arch/arm/cpu/arm926ejs/cache.c, there implements a real flush_cache()
function as well. That means the original code for ARM1136 &amp; ARM926ejs
in weak flush_cache() of arch/arm/lib/cache.c is totally useless.

So in this patch remove such code in flush_cache() and only call
flush_dcache_range().

Signed-off-by: Josh Wu &lt;josh.wu@atmel.com&gt;
</content>
</entry>
<entry>
<title>ARM: cache: add an empty stub function for invalidate/flush dcache</title>
<updated>2015-08-13T00:47:47Z</updated>
<author>
<name>Wu, Josh</name>
<email>Josh.wu@atmel.com</email>
</author>
<published>2015-07-27T03:40:16Z</published>
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<id>urn:sha1:387871a10edc777a5d94bfdbd6b86e493991826e</id>
<content type='text'>
Since some driver like ohci, lcd used dcache functions. But some ARM
cpu don't implement the invalidate_dcache_range()/flush_dcache_range()
functions.

To avoid compiling errors this patch adds an weak empty stub function
for all ARM cpu in arch/arm/lib/cache.c.
And ARM cpu still can implemnt its own cache functions on the cpu folder.

Signed-off-by: Josh Wu &lt;josh.wu@atmel.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
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