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<title>u-boot.git/arch/arm/lib, branch v2018.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/lib?h=v2018.07</id>
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<updated>2018-06-19T11:31:45Z</updated>
<entry>
<title>ARM: image: Add option for ignoring ep bit 3</title>
<updated>2018-06-19T11:31:45Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut@gmail.com</email>
</author>
<published>2018-06-13T04:13:32Z</published>
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<id>urn:sha1:7f13b374fd8fa59f694a1127a79f9bfc3891ef0d</id>
<content type='text'>
Add option to the booti_setup() which indicates to it that the caller
requires the image to be relocated to the beginning of the RAM and
that the information whether the image can be located anywhere in RAM
at 2 MiB aligned boundary or not is to be ignored. This is useful ie.
in case the Image is wrapped in another envelope, ie. fitImage and not
relocating it but moving it would corrupt the envelope.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Bin Chen &lt;bin.chen@linaro.org&gt;
Cc: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Cc: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-By: Bin Chen &lt;bin.chen@linaro.org&gt;
</content>
</entry>
<entry>
<title>arm: Do not clear LR on exception in SPL</title>
<updated>2018-06-18T18:43:13Z</updated>
<author>
<name>Andrew F. Davis</name>
<email>afd@ti.com</email>
</author>
<published>2018-06-11T19:04:17Z</published>
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<id>urn:sha1:a1b73c18724eb8cb75f7a60d851578d933c78095</id>
<content type='text'>
When an exception or interrupt occurs the link register (LR) may
contain the source of the exception, although we do not print the
value it may still be extracted with a debugger. When in SPL we
loop on getting and exception, but use a linking branch, which
over-writes the LR value, use a regular branch instruction here.

Signed-off-by: Andrew F. Davis &lt;afd@ti.com&gt;
</content>
</entry>
<entry>
<title>arm: print instructions pointed to by pc</title>
<updated>2018-05-24T02:06:41Z</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>xypron.glpk@gmx.de</email>
</author>
<published>2018-05-15T17:42:23Z</published>
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<id>urn:sha1:bd2a13f32959a851d43d9681d9dc9b8bb3eec398</id>
<content type='text'>
If an exception occurs in a loaded image and the relocation offset is
unknown, it is helful to know the instructions pointed to by the
program counter. This patch adds the missing output.

A possible output is:
    Code: e1c560d0 e12fff1e e120077b e12fff1e (e7f7defb)

The parentheses indicate the instruction causing the exception.

The output can be disassembled using the decodecode script provided
by the Linux kernel project.

Signed-off-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
</content>
</entry>
<entry>
<title>bootm: fix 'memory-fixup' for vxWorks boot</title>
<updated>2018-05-11T00:38:34Z</updated>
<author>
<name>Hannes Schmelzer</name>
<email>hannes.schmelzer@br-automation.com</email>
</author>
<published>2018-05-04T08:49:11Z</published>
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<id>urn:sha1:7f1cb1d588789585aa962250fda4c3e095901c5b</id>
<content type='text'>
The check for having a memory node within the fdt blob is made wrong, we
fix this here.

Signed-off-by: Hannes Schmelzer &lt;hannes.schmelzer@br-automation.com&gt;
</content>
</entry>
<entry>
<title>arm: v7R: Add support for enabling caches</title>
<updated>2018-05-07T19:53:29Z</updated>
<author>
<name>Lokesh Vutla</name>
<email>lokeshvutla@ti.com</email>
</author>
<published>2018-04-26T12:51:31Z</published>
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<id>urn:sha1:a43d46a73cb2c40481791cb292b8eb0b5a80d55e</id>
<content type='text'>
Cache maintenance procedure is same for v7A and v7R
processors. So re-use cache-cp15.c file except for
mmu parts.

Tested-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Signed-off-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>arm: v7: Kconfig: Introduce SYS_ARM_CACHE_CP15</title>
<updated>2018-05-07T19:53:28Z</updated>
<author>
<name>Lokesh Vutla</name>
<email>lokeshvutla@ti.com</email>
</author>
<published>2018-04-26T12:51:28Z</published>
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<id>urn:sha1:f4bcd767bdc0925528e66974af7575a5796aaab7</id>
<content type='text'>
Certain ARM architectures like ARMv7-A, ARMv7-R has support for
enabling caches using CP15 registers. To have a common support
for all these architectures, introduce a Kconfig symbol
SYS_ARM_CACHE_CP15 that selects cache-cp15.c

Tested-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Signed-off-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
</content>
</entry>
<entry>
<title>arm: v7: Kconfig: Rename CPU_V7 as CPU_V7A</title>
<updated>2018-05-07T19:53:24Z</updated>
<author>
<name>Lokesh Vutla</name>
<email>lokeshvutla@ti.com</email>
</author>
<published>2018-04-26T12:51:26Z</published>
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<id>urn:sha1:acf1500138bb6b0496fe09d6bffdf8eac3d6ecab</id>
<content type='text'>
Currently CPU_V7 kconfig symbol supports only ARMv7A architectures under
armv7 folder. This led to a misconception of creating separate folders
for armv7m and armv7r. There is no reason to create separate folder for
other armv7 based architectures when it can co-exist with few Kconfig
symbols.

As a first step towards a common folder, rename CPU_V7 as CPUV7A. Later
separate Kconfig symbols can be added for CPU_V7R and CPU_V7M and
can co exist in the same folder.

Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Tested-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Suggested-by: Alexander Graf &lt;agraf@suse.de&gt;
Signed-off-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
</content>
</entry>
<entry>
<title>SPDX: Convert all of our multiple license tags to Linux Kernel style</title>
<updated>2018-05-07T14:24:31Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-05-06T22:27:01Z</published>
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<id>urn:sha1:4549e789c1d58a8c48e8a20f1b4bdb83e978c954</id>
<content type='text'>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have multiple licenses (in
these cases, dual license) declared in the SPDX-License-Identifier tag.
In this case we change from listing "LICENSE-A LICENSE-B" or "LICENSE-A
or LICENSE-B" or "(LICENSE-A OR LICENSE-B)" to "LICENSE-A OR LICENSE-B"
as per the Linux Kernel style document.  Note that parenthesis are
allowed so when they were used before we continue to use them.

Reviewed-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>SPDX: Convert all of our single license tags to Linux Kernel style</title>
<updated>2018-05-07T13:34:12Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-05-06T21:58:06Z</published>
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<id>urn:sha1:83d290c56fab2d38cd1ab4c4cc7099559c1d5046</id>
<content type='text'>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR</title>
<updated>2018-04-27T18:54:48Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-04-18T17:50:47Z</published>
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<id>urn:sha1:d024236e5a31a2b4b82cbcc98b31b8170fc88d28</id>
<content type='text'>
We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added
that line "just in case" during development and never dropped it.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
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