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<title>u-boot.git/arch/arm/lib, branch v2024.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/lib?h=v2024.04</id>
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<updated>2024-01-12T02:19:25Z</updated>
<entry>
<title>arm: spl: Use separate fault handlers instead of a single common one</title>
<updated>2024-01-12T02:19:25Z</updated>
<author>
<name>Csókás Bence</name>
<email>csokas.bence@prolan.hu</email>
</author>
<published>2023-12-19T13:33:18Z</published>
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<id>urn:sha1:29f390bbd5b463676065134e3e58f7a50dbfd8ec</id>
<content type='text'>
It may be necessary to set breakpoints etc. on a specific fault handler in SPL.
Add a Kconfig option to separate the different handlers into their own individual infinite loops.

Signed-off-by: Csókás Bence &lt;csokas.bence@prolan.hu&gt;
</content>
</entry>
<entry>
<title>bootm: Adjust arguments of boot_os_fn</title>
<updated>2023-12-21T21:07:52Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2023-12-16T03:14:13Z</published>
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<id>urn:sha1:a48336e5ea19ca0d32dfff1c4eaeececa8d2f570</id>
<content type='text'>
Adjust boot_os_fn to use struct bootm_info instead of the separate
argc, argv and image parameters. Update the handlers accordingly. Few
of the functions make use of the arguments, so this improves code size
slightly.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>arm: semihosting: Support semihosting fallback on 32-bit ARM</title>
<updated>2023-11-10T17:52:33Z</updated>
<author>
<name>Sean Anderson</name>
<email>sean.anderson@seco.com</email>
</author>
<published>2023-10-27T20:40:15Z</published>
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<id>urn:sha1:47cfdb2192b1f8cb5061bde53fcce562afaeadf2</id>
<content type='text'>
Add support for a semihosting fallback on 32-bit ARM. The assembly is
lightly adapted from the irq return code, except there is no offset
since lr already points to the correct instruction. The C side is mostly
like ARM64, except we have fewer cases to deal with.

Signed-off-by: Sean Anderson &lt;sean.anderson@seco.com&gt;
</content>
</entry>
<entry>
<title>arm: semihosting: Fix returning from traps on ARMv6 and lower</title>
<updated>2023-11-10T17:52:28Z</updated>
<author>
<name>Sean Anderson</name>
<email>sean.anderson@seco.com</email>
</author>
<published>2023-10-27T20:40:14Z</published>
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<id>urn:sha1:6ef83ab6be8978ab85a7d8967e9585ddf5f2bbbd</id>
<content type='text'>
U-Boot runs in supervisor mode. On ARMv6 and lower, software interrupts
are taken in supervisor mode. When entering an interrupt, the link
register is set to the address of the next instruction. However, if we
are already in supervisor mode, this clobbers the link register. The
debugger can't help us, since by the time it notices we've taken a
software interrupt, the link register is already gone. Work around this
by moving the return address to another register.

Signed-off-by: Sean Anderson &lt;sean.anderson@seco.com&gt;
</content>
</entry>
<entry>
<title>arm: Fix software interrupt handler</title>
<updated>2023-11-10T16:55:17Z</updated>
<author>
<name>Sean Anderson</name>
<email>sean.anderson@seco.com</email>
</author>
<published>2023-10-27T20:40:13Z</published>
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<id>urn:sha1:298c26c5c7f4105f4e421d227009baeba5c59678</id>
<content type='text'>
When we take a software interrupt, we are already in supervisor mode.
get_bad_stack assumes we are not in supervisor mode so it can clobber
the stack pointer. This causes us to have an invalid stack once that
macro finishes. Revert back to the get_bad_stack_swi macro which was
previously removed.

Fixes: 41623c91b09 ("arm: move exception handling out of start.S files")
Signed-off-by: Sean Anderson &lt;sean.anderson@seco.com&gt;
</content>
</entry>
<entry>
<title>spl: Use SYS_MALLOC_F instead of SYS_MALLOC_F_LEN</title>
<updated>2023-10-06T18:38:12Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2023-09-26T14:14:27Z</published>
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<id>urn:sha1:3d6d50751469fbadec3e34fbb6d06f21746619dd</id>
<content type='text'>
Use the new SPL/TPL/VPL_SYS_MALLOC_F symbols to determine whether the
malloc pool exists.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Sean Anderson &lt;sean.anderson@seco.com&gt;
</content>
</entry>
<entry>
<title>common: Drop linux/printk.h from common header</title>
<updated>2023-09-24T13:54:57Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2023-09-15T00:21:46Z</published>
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<id>urn:sha1:1e94b46f73cedcebbff73799203f3266c5b28d90</id>
<content type='text'>
This old patch was marked as deferred. Bring it back to life, to continue
towards the removal of common.h

Move this out of the common header and include it only where needed.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'v2023.10-rc3' into next</title>
<updated>2023-08-21T21:32:17Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-08-21T21:32:17Z</published>
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<id>urn:sha1:7e6e40c572332b3835c5cb48a08e1d8d404c871c</id>
<content type='text'>
Prepare v2023.10-rc3

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>arm: Use builtins for ffs/fls</title>
<updated>2023-08-17T20:39:20Z</updated>
<author>
<name>Sean Anderson</name>
<email>sean.anderson@seco.com</email>
</author>
<published>2023-07-31T21:27:33Z</published>
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<id>urn:sha1:726a802fdaf1ffb4ca95ebf6910a738781137ef5</id>
<content type='text'>
Since ARMv5, the clz instruction allows for efficient implementation of
ffs/fls with builtins. Until ARMv7 (with Thumb-2), this instruction is
only available in ARM mode. LTO makes it difficult to force specific
functions to be in ARM mode, as it is effectively a form of very
aggressive inlining. To work around this, fls/ffs are implemented in
assembly for ARMv5 and ARMv6 when compiling U-Boot in Thumb mode.
Overall, this saves around 75 bytes per call.

This code is synced with v5.15 of the Linux kernel.

Signed-off-by: Sean Anderson &lt;sean.anderson@seco.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>arm64: smccc: add support for SMCCCv1.2 x0-x17 registers</title>
<updated>2023-08-08T14:22:03Z</updated>
<author>
<name>Abdellatif El Khlifi</name>
<email>abdellatif.elkhlifi@arm.com</email>
</author>
<published>2023-08-04T13:33:37Z</published>
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<id>urn:sha1:d99873517907b806fe35f5a009c2b729c39d5808</id>
<content type='text'>
add support for x0-x17 registers used by the SMC calls

In SMCCC v1.2 [1] arguments are passed in registers x1-x17.
Results are returned in x0-x17.

This work is inspired from the following kernel commit:

arm64: smccc: Add support for SMCCCv1.2 extended input/output registers

[1]: https://documentation-service.arm.com/static/5f8edaeff86e16515cdbe4c6?token=

Signed-off-by: Abdellatif El Khlifi &lt;abdellatif.elkhlifi@arm.com&gt;
Reviewed-by: Ilias Apalodimas &lt;ilias.apalodimas@linaro.org&gt;
Reviewed-by: Jens Wiklander &lt;jens.wiklander@linaro.org&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
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