u-boot.git/arch/arm/mach-imx/mx7ulp/scg.c, branch main

arm: mach: imx: Remove duplicate newlines

2024-07-15T18:12:17Z

Drop all duplicate newlines. No functional change. Signed-off-by: Marek Vasut

Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"

2024-05-20T19:35:03Z

As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman Signed-off-by: Tom Rini

Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""

2024-05-19T14:16:36Z

When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman Signed-off-by: Tom Rini

arm: imx: Remove and add needed includes

2024-05-06T21:06:34Z

Remove from all mach-imx, CPU specific sub-directories and include/asm/arch-mx* files and when needed add missing include files directly. Acked-by: Peng Fan Signed-off-by: Tom Rini

common: Drop linux/delay.h from common header

2020-05-19T01:19:23Z

Move this uncommon header out of the common header. Signed-off-by: Simon Glass

common: Drop log.h from common header

2020-05-19T01:19:18Z

Move this header out of the common header. Signed-off-by: Simon Glass

mx7ulp: scg: Remove unnused scg_a7_apll_init()

2019-12-06T11:05:08Z

scg_a7_apll_init() is not called anywhere, so remove such dead code Signed-off-by: Fabio Estevam

i.MX7ULP: Change clock rate calculation for NIC1 BUS and EXT

2019-10-08T14:35:16Z

On i.MX7ULP B0, there is change in NIC clock dividers architecture. On A0, the NIC1 BUS and EXT dividers were in a chain with NIC1 DIV, but on B0 they are parallel with NIC1 DIV. So now the dividers are independent. This patch modifies the scg_nic_get_rate function according to this change. Signed-off-by: Ye Li Acked-by: Peng Fan

i.MX7ULP: Set A7 core frequency to 500Mhz for B0 chip

2019-10-08T14:35:16Z

The normal target frequency for ULP A7 core is 500Mhz, but now ROM set the core frequency to 413Mhz. So change it to 500Mhz in u-boot. Signed-off-by: Ye Li Signed-off-by: Peng Fan

i.MX7ULP: Fix SPLL/APLL clock rate calculation issue

2019-10-08T14:35:16Z

The num/denom is a float value, but in the calculation it is convert to integer 0, and cause the result wrong. Signed-off-by: Ye Li Signed-off-by: Peng Fan