u-boot.git/arch/arm/mach-k3/include, branch main

arm: k3: select tifsstub via board_fit_config_name_match

2026-07-16T18:03:40Z

TI K3 AM62x/AM62Ax/AM62Px boards carry two or three mutually-exclusive tifsstub variants in their tispl.bin FIT images, all at the same load address. The existing approach loads every variant and then discards the wrong ones at runtime via a *p_size = 0 hack in board_fit_image_post_process(). Switch to selecting the appropriate FIT configuration up front via board_fit_config_name_match() so only the correct tifsstub is loaded in the first place. board_fit_config_name_match() is invoked by the R5 SPL during FIT config selection. get_device_type() is a simple register read that is available at that point, so the security state can be determined early. The matching logic is factored into k3_fit_config_match_security_state() in arch/arm/mach-k3/common.c so it can be shared by any K3 board that wants this scheme. It matches configurations by a suffix appended to the description string: -hs-se -> HS-SE (K3_DEVICE_TYPE_HS_SE) -hs-fs -> HS-FS (K3_DEVICE_TYPE_HS_FS) -gp -> GP (K3_DEVICE_TYPE_GP) Configurations without a security-state suffix (e.g. u-boot.img) do not match and fall through to the DTS-specified default config naturally. Each TI EVM board defines its board_fit_config_name_match() as a thin wrapper around the shared helper: - board/ti/am62x/evm.c (AM625 SK: hs-se, hs-fs, gp) - board/ti/am62ax/evm.c (AM62A SK: hs-se, hs-fs, gp) - board/ti/am62px/evm.c (AM62P SK: hs-se, hs-fs, gp) FIT configurations are split per security state in: - arch/arm/dts/k3-am625-sk-binman.dtsi (ti-falcon, ti-spl, ti-spl_unsigned: conf-hs-se/conf-hs-fs/conf-gp) - arch/arm/dts/k3-am62a-sk-binman.dtsi (ti-falcon, ti-spl: conf-hs-se/conf-hs-fs; no GP variant on AM62A) - arch/arm/dts/k3-am62p-sk-binman.dtsi (ti-falcon, ti-spl: conf-hs-se/conf-hs-fs; no GP variant on AM62P) The runtime filter in board_fit_image_post_process() is intentionally left in place. It becomes redundant once every board using the AM62x family dtsi files migrates to per-state configurations. The dtsi for phytec phycore and toradex verdin boards is updated by separate patches in this series, and the now-redundant runtime filter is removed by the final patch in the series. Signed-off-by: Aristo Chen Reviewed-by: Anshul Dalal

arm: mach-k3: arm: mach-k3: Add writel_verify macro for register write verification

2026-05-11T18:32:00Z

Add a helper macro to write and verify a 32-bit value to a memory-mapped register. This is essential for hardware errata workarounds that require confirmation that register writes have taken effect before proceeding with initialization. Signed-off-by: Udit Kumar

arm: mach-k3: arm64-mmu: add mapping for PCIe 4 GB Address Windows

2026-03-09T15:35:18Z

The PCIe Controllers in the K3 SoCs have 4 GB Address Windows in the 64-bit address space to map System (CPU) Addresses to PCIe Bus Addresses. The physical addresses for these Address Windows across PCIe instances across SoCs is as follows: +--------+----------------+----------------+----------------+----------------+ | SoC | PCIe0 | PCIe1 | PCIe2 | PCIe3 | +--------+----------------+----------------+----------------+----------------+ | AM64 | 0x6_0000_0000 | NA | NA | NA | | J722S | 0x6_0000_0000 | NA | NA | NA | | AM68 | NA | 0x41_0000_0000 | NA | NA | | J7200 | NA | 0x41_0000_0000 | NA | NA | | J721S2 | NA | 0x41_0000_0000 | NA | NA | | J742S2 | 0x40_0000_0000 | 0x41_0000_0000 | NA | NA | | AM69 | 0x40_0000_0000 | 0x41_0000_0000 | 0x42_0000_0000 | 0x43_0000_0000 | | J721E | 0x40_0000_0000 | 0x41_0000_0000 | 0x42_0000_0000 | 0x43_0000_0000 | | J784S4 | 0x40_0000_0000 | 0x41_0000_0000 | 0x42_0000_0000 | 0x43_0000_0000 | +--------+----------------+----------------+----------------+----------------+ Two regions for a 1:1 mapping from virtual addresses to physical addresses catering to all of the above will be required, which are: 1. For AM64 and J722S SoCs => Start: 0x6_0000_0000 Size: 0x1_0000_0000 2. For AM68, AM69, J7200, J721E, J721S2, J742S2 and J784S4 SoCs => Start: 0x40_0000_0000 Size: 0x4_0000_0000 Since the 'Flash Peripherals' region from 0x5_0000_0000 to 0x8_7FFF_FFFF includes the mapping for AM64 and J722S SoCs, only the second region mentioned above needs to be added. Hence, add the region to support 64-bit address space for PCIe. Signed-off-by: Siddharth Vadapalli Fixes: 79f3e77133bd ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream")

mach-k3: am64x: add support for speed grades

2026-01-29T15:59:53Z

With the support for common speed grade configuration added in commit 65a6b83a9b7f ("mach-k3: refactor A53 speed grade clock-rate fixup"), this patch extends the support to AM64x SoCs. Signed-off-by: Anshul Dalal

ti: k3: abstract common fdt api for reserved mem fixups

2025-12-16T17:36:48Z

The usage of fdt_fixup_reserved is repeated for ATF and OP-TEE for multiple platforms, this patch creates a single fdt API for fixing up the reserved-memory node with added error handling. All k3 platforms already share a common tispl template which ensures binaries are loaded as per the respective CONFIG_*_LOAD_ADDR. And the provided new_size for the fixup is overridden by the size from fdt node anyways. This allows for safe abstraction of the reserved memory fixups for all current platforms. fdt_fixup_reserved now abstracts the ATF and OP-TEE fixups by calling the renamed static fdt_fixup_reserved_memory function with the required parameters. Signed-off-by: Anshul Dalal

mach-k3: am62a: add support for speed grades

2025-11-12T15:42:17Z

Speed grades indicate the maximum operating frequency of any core on the SoC. This patch adds support for the same to AM62a, this allows the A53 core to be started with the correct frequency by the R5 SPL. Reference: Device Speed Grades (Table 6-1) in AM62a7 Datasheet https://www.ti.com/lit/ds/symlink/am62a7.pdf (Page#82) Signed-off-by: Anshul Dalal

mach-k3: refactor A53 speed grade clock-rate fixup

2025-11-12T15:42:17Z

The K3 ARM64 rproc driver uses the "assigned-clock-rates" value in the respective "/a53@0" node to properly configure the clocks for the A53 core. Although the clock value in the DT node might need to be fixed based on SoC's speed grade at runtime. Certain SoCs such as AM62p and AM62x already had this implemented, this patch moves the common code to common.c to avoid duplication and simplify speed grade handling. The logic to detect the correct entry in the "assigned-clock-rates" property has also changed. Where we earlier relied on per SoC specific device and clock IDs for the A53 core, we now use the "clock-names" property which is device agnostic. Signed-off-by: Anshul Dalal Reviewed-by: Aniket Limaye

mach-k3: map all banks using mem_map_from_dram_banks

2025-10-22T18:05:52Z

The static memory map for K3 (k3_mem_map) only maps the first DRAM bank and therefore doesn't scale for platforms with multiple memory banks. This patch modifies enable_caches to add mem_map_from_dram_banks which appends all the memory banks to k3_mem_map before calling mmu_setup. Signed-off-by: Anshul Dalal Tested-by: Wadim Egorov

Merge patch series "arm: mach-k3: am64x: Add reset cause for cpuinfo"

2025-09-12T19:49:34Z

Steffen Kothe says: AM64X hereby receives support for reset reason printing during boot. Unfortunately does the AM64X register mapping slighlty differ from the AM62X. WDT and PORZ are not part of the reset source register, but the mapping remains the same for all other causes. To prevent ifdef/else constructs, I decided to follow a simple copy/paste approach and adjusted the logic accordingly. Link: https://lore.kernel.org/r/20250831151706.404373-1-steffen.kothe@skothe.net

arm: mach-k3: am64_hardware.h: Add CTRLMMR_MCU_RST_SRC reset cause bit mappings

2025-09-12T18:30:08Z

AM64X SoCs use similar but not identical bit mappings like the AM62X family. In detail does the AM64X not support PORZ and WDT as reset caused. Add the mapping according to the technical reference manual into the SoC specific header. Signed-off-by: Steffen Kothe Reviewed-by: Bryan Brattlof