u-boot.git/arch/arm/mach-mvebu/include, branch master Unnamed repository; edit this file 'description' to name the repository. arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD 2024-10-11T17:44:47+00:00 Simon Glass sjg@chromium.org 2024-09-30T01:49:46+00:00 bef9fdbed2e525ce9264d2ae2fbcb37db7472052 Use the new symbol to refer to any 'SPL' build, including TPL and VPL Signed-off-by: Simon Glass <sjg@chromium.org> 
Use the new symbol to refer to any 'SPL' build, including TPL and VPL

Signed-off-by: Simon Glass <sjg@chromium.org>
arm: mvebu: a38x: Add optional support for using old DDR3 training code 2024-07-08T06:20:58+00:00 Marek Behún kabel@kernel.org 2024-06-18T15:34:38+00:00 aff4ea11d18d71fd5c87b5503e99284cc2927502 Add optional support for using old DDR3 training code from 2017. The code lives in drivers/ddr/marvell/a38x/old/. To prevent symbol clashing with new DDR3 training code, a special header which renames all clashing symbols via macros is included and the symbols are prefixed with 'old_'. If old DDR3 training support is selected for a board, then the SPL initialization code calls a new function board_use_old_ddr3_training() to check whether it should use old DDR3 training code. The default weak implementation returns false, defaulting to new DDR3 training code. Boards that wish to support this need to select the ARMADA_38X_SUPPORT_OLD_DDR3_TRAINING config option and implement the old version of DDR topology provider, ddr3_get_topology_map(). Signed-off-by: Marek Behún <kabel@kernel.org> 
Add optional support for using old DDR3 training code from 2017.

The code lives in drivers/ddr/marvell/a38x/old/. To prevent symbol
clashing with new DDR3 training code, a special header which renames all
clashing symbols via macros is included and the symbols are prefixed
with 'old_'.

If old DDR3 training support is selected for a board, then the SPL
initialization code calls a new function
  board_use_old_ddr3_training()
to check whether it should use old DDR3 training code. The default
weak implementation returns false, defaulting to new DDR3 training code.

Boards that wish to support this need to select the
  ARMADA_38X_SUPPORT_OLD_DDR3_TRAINING
config option and implement the old version of DDR topology provider,
ddr3_get_topology_map().

Signed-off-by: Marek Behún <kabel@kernel.org>
arm: Drop <common.h> from remaining header files 2023-11-07T19:50:52+00:00 Tom Rini trini@konsulko.com 2023-11-01T16:28:23+00:00 e8acfd2bb223d8e21fb4e58c674a661043bcf963 None of these header files need to include <common.h> so we can just drop that entirely. Signed-off-by: Tom Rini <trini@konsulko.com> 
None of these header files need to include <common.h> so we can just
drop that entirely.

Signed-off-by: Tom Rini <trini@konsulko.com>
arm: mvebu: Define all options for AXP BOOT_FROM_* macros 2023-03-30T05:05:20+00:00 Pali Rohár pali@kernel.org 2023-03-29T19:03:35+00:00 babc1806c2974bf92b331b1830c084677599321c Definitions are according to the MV78460 Hardware Specifications. Signed-off-by: Pali Rohár <pali@kernel.org> Tested-by: Tony Dinh <mibodhi@gmail.com> Tested-by: Martin Rowe <martin.p.rowe@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> 
Definitions are according to the MV78460 Hardware Specifications.

Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Tony Dinh <mibodhi@gmail.com>
Tested-by: Martin Rowe <martin.p.rowe@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
arm: mvebu: Define all BOOTROM_ERR_MODE_* macros 2023-03-30T05:05:20+00:00 Pali Rohár pali@kernel.org 2023-03-29T19:03:34+00:00 3ac1a064e735a940c05089dee6b86377c65fa890 A385 BootROM fills into bits [31:28] of register 0x182d0 tracing value, which represents in which state BootROM currently is. BootROM fills one of the possible values: 0x2 (CPU initialization), 0x3 (UART detection), 0x6 (UART booting), 0x8 (PCI Express booting), 0x9 (parallel or SPI NOR booting), 0xA (parallel or SPI NAND booting), 0xB (SATA booting) and 0xE (SD / eMMC booting). Meaning of these values matches TRACE_* macros from Marvell soc_spec.h file: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/blob/u-boot-2013.01-armada-18.06/tools/marvell/doimage_mv/soc_spec.h Signed-off-by: Pali Rohár <pali@kernel.org> Tested-by: Tony Dinh <mibodhi@gmail.com> Tested-by: Martin Rowe <martin.p.rowe@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> 
A385 BootROM fills into bits [31:28] of register 0x182d0 tracing value,
which represents in which state BootROM currently is. BootROM fills one
of the possible values: 0x2 (CPU initialization), 0x3 (UART detection),
0x6 (UART booting), 0x8 (PCI Express booting), 0x9 (parallel or SPI NOR
booting), 0xA (parallel or SPI NAND booting), 0xB (SATA booting) and 0xE
(SD / eMMC booting).

Meaning of these values matches TRACE_* macros from Marvell soc_spec.h file:
https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/blob/u-boot-2013.01-armada-18.06/tools/marvell/doimage_mv/soc_spec.h

Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Tony Dinh <mibodhi@gmail.com>
Tested-by: Martin Rowe <martin.p.rowe@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
arm: mvebu: Define all options for A38x BOOT_FROM_* macros 2023-03-30T05:05:20+00:00 Pali Rohár pali@kernel.org 2023-03-29T19:03:33+00:00 4f67eba7331025029b22d66f2f1c7e2632ac61c3 Disassembling A385 BootROM binary reveal how BootROM interprets strapping pins for Boot Device Mode. All possible options are: 0x00..0x07 -> Parallel NOR 0x08..0x15 -> Parallel NAND 0x16..0x17 -> Parallel NOR 0x18..0x25 -> Parallel NAND 0x26..0x27 -> SPI NAND 0x28..0x29 -> UART xmodem 0x2a..0x2b -> SATA 0x2c..0x2d -> PCI Express 0x2e..0x2f -> Parallel NOR 0x30..0x31 -> SD / eMMC 0x32..0x39 -> SPI NOR 0x3a..0x3c -> Parallel NOR 0x3d..0x3e -> UART debug console 0x3f -> Invalid Note that Boot Device Mode Options in A38x Hardware Specifications is incomplete. Signed-off-by: Pali Rohár <pali@kernel.org> Tested-by: Tony Dinh <mibodhi@gmail.com> Tested-by: Martin Rowe <martin.p.rowe@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> 
Disassembling A385 BootROM binary reveal how BootROM interprets strapping
pins for Boot Device Mode. All possible options are:

0x00..0x07 -> Parallel NOR
0x08..0x15 -> Parallel NAND
0x16..0x17 -> Parallel NOR
0x18..0x25 -> Parallel NAND
0x26..0x27 -> SPI NAND
0x28..0x29 -> UART xmodem
0x2a..0x2b -> SATA
0x2c..0x2d -> PCI Express
0x2e..0x2f -> Parallel NOR
0x30..0x31 -> SD / eMMC
0x32..0x39 -> SPI NOR
0x3a..0x3c -> Parallel NOR
0x3d..0x3e -> UART debug console
0x3f       -> Invalid

Note that Boot Device Mode Options in A38x Hardware Specifications is
incomplete.

Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Tony Dinh <mibodhi@gmail.com>
Tested-by: Martin Rowe <martin.p.rowe@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
arm: mvebu: Convert BOOT_FROM_* constants to function macros 2023-03-30T05:05:20+00:00 Pali Rohár pali@kernel.org 2023-03-29T19:03:32+00:00 7ba084c7f81f5b31125fdfdefd8e105dbd0366fe This allows to merge BOOT_FROM_MMC and BOOT_FROM_MMC_ALT constants to one macro. And also allows to extend other BOOT_FROM_* macros for other variants. Signed-off-by: Pali Rohár <pali@kernel.org> Tested-by: Tony Dinh <mibodhi@gmail.com> Tested-by: Martin Rowe <martin.p.rowe@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> 
This allows to merge BOOT_FROM_MMC and BOOT_FROM_MMC_ALT constants to one
macro. And also allows to extend other BOOT_FROM_* macros for other
variants.

Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Tony Dinh <mibodhi@gmail.com>
Tested-by: Martin Rowe <martin.p.rowe@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
arm: mvebu: Remove A38x BOOT_FROM_SATA 0x22 constant 2023-03-30T05:05:20+00:00 Pali Rohár pali@kernel.org 2023-03-29T19:03:31+00:00 4642bb3e76cfc3fe765dbe3174ceaffba94ea1f2 A385 BootROM treats strapping configuration 0x22 as SPI-NAND. So remove incorrect definition 0x22 as SATA. SATA on A385 has configuration 0x2A. Signed-off-by: Pali Rohár <pali@kernel.org> Tested-by: Tony Dinh <mibodhi@gmail.com> Tested-by: Martin Rowe <martin.p.rowe@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> 
A385 BootROM treats strapping configuration 0x22 as SPI-NAND. So remove
incorrect definition 0x22 as SATA. SATA on A385 has configuration 0x2A.

Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Tony Dinh <mibodhi@gmail.com>
Tested-by: Martin Rowe <martin.p.rowe@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
arm: mvebu: Remove A38x BOOT_FROM_UART_ALT 0x3f constant 2023-03-30T05:05:20+00:00 Pali Rohár pali@kernel.org 2023-03-29T19:03:30+00:00 2360409d9c1defb329cdcf8108ddb3501c467a93 A385 BootROM treats strapping configuration 0x3f as invalid. When booting fails (e.g. because of invalid configuration) then BootROM fallbacks to UART booting. Detecting BootROM fallback to UART booting is implemented in U-Boot since commit 2fd4284051e3 ("ARM: mach-mvebu: handle fall-back to UART boot"). So there is no need to define BOOT_FROM_UART_ALT constant and special handling for it anymore, remove it. This change effectively revers commit f3a88e2ca17a ("arm: mvebu: fix boot from UART on ClearFog Base"). Signed-off-by: Pali Rohár <pali@kernel.org> Tested-by: Tony Dinh <mibodhi@gmail.com> Tested-by: Martin Rowe <martin.p.rowe@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> 
A385 BootROM treats strapping configuration 0x3f as invalid. When booting
fails (e.g. because of invalid configuration) then BootROM fallbacks to
UART booting.

Detecting BootROM fallback to UART booting is implemented in U-Boot since
commit 2fd4284051e3 ("ARM: mach-mvebu: handle fall-back to UART boot").

So there is no need to define BOOT_FROM_UART_ALT constant and special
handling for it anymore, remove it.

This change effectively revers commit f3a88e2ca17a ("arm: mvebu: fix boot
from UART on ClearFog Base").

Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Tony Dinh <mibodhi@gmail.com>
Tested-by: Martin Rowe <martin.p.rowe@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
arm: mvebu: Define SPL memory maps 2023-03-01T05:39:18+00:00 Pali Rohár pali@kernel.org 2023-02-03T21:26:37+00:00 e00008939f4b6bb255a219b1aba710d67818d822 In SPL are active memory maps set by the BootROM. Define them in cpu.h file to the correct values. Some peripherals are not mapped at all. Signed-off-by: Pali Rohár <pali@kernel.org> 
In SPL are active memory maps set by the BootROM. Define them in cpu.h file
to the correct values. Some peripherals are not mapped at all.

Signed-off-by: Pali Rohár <pali@kernel.org>