u-boot.git/arch/arm/mach-socfpga/include, branch master

Replace TARGET namespace and cleanup properly

2026-02-14T17:06:46Z

TARGET namespace is for machines / boards / what-have-you that building U-Boot for. Simply replace from TARGET to ARCH make things more clear and proper for ALL SoCFPGA. Signed-off-by: Brian Sune Reviewed-by: Tien Fong Chee # Conflicts: # drivers/ddr/altera/Makefile

arch: arm: socfpga: Configure USB3 System Manager registers

2025-09-30T06:45:37Z

For successful reset staggering pulse operation, reset pulse override bit is set. Port overcurrent bit 1, which in reality reflects PIPE power present signal is set to avoid giving false information of Vbus status to HPS controller. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee

arm: socfpga: mailbox: Remove CONFIG_CADENCE_QSPI guard from QSPI mailbox API declarations

2025-09-30T06:29:54Z

The QSPI mailbox API function declarations (mbox_qspi_close and mbox_qspi_open) in mailbox_s10.h were guarded by CONFIG_CADENCE_QSPI preprocessor conditional. This prevented their prototypes from being visible to code that may use the stub implementations when CONFIG_CADENCE_QSPI is disabled. Remove the CONFIG_CADENCE_QSPI preprocessor conditional so these functions are always declared, regardless of the configuration. This avoids potential build or linkage errors when stubs are used. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee

arm: socfpga: Define Use FPGA switch handoff section size for Agilex5

2025-09-30T06:29:53Z

Agilex5 FPGA switch section in the handoff data is larger by 32 bytes than the default value as these extra sections contains I3C0 and I3C1 register offsets and values with 4 bytes each. This requires 4 more times of reading the FPGA switch section of the handoff data to fully populate the handoff data table in the memory during runtime. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee

ddr: altera: Add DDR driver for Agilex7 M-series

2025-08-08T14:20:54Z

This is for new platform enablement for Agilex7 M-series. Add DDR driver for Agilex7 M-series. This driver is designed to support DDR and HBM memory. The official HBM handoff is not ready yet, therefore hardcoded handoff is used for HBM driver validation on mUDV board. Signed-off-by: Tingting Meng Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee

clk: altera: Add clock support for Agilex7 M-series

2025-08-08T14:20:53Z

Agilex7 M-series reuse the clock driver from Agilex. Signed-off-by: Tingting Meng Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee

arch: arm: mach-socfpga: Update handoff settings for Agilex7 M-series

2025-08-08T14:20:52Z

Handoff settings updated for new platform Agilex7 M-series. Signed-off-by: Tingting Meng Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee

arch: arm: mach-socfpga: Add Agilex7 M-series mach-socfgpa enablement

2025-08-08T14:20:51Z

Add platform related files for new platform Agilex7 M-series. Signed-off-by: Tingting Meng Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee

arm: socfpga: soc64: Perform warm reset after L2 reset in SPL

2025-08-08T14:20:50Z

SPL checks for a magic word in the system manager's scratch register to determine if an L2 reset has occurred. If detected, SPL places all slave CPUs (CPU1–3) into WFI mode. The master CPU (CPU0) then initiates a warm reset by writing to the RMR_EL3 system register and also enters WFI mode. This warm reset flow is handled entirely within the HPS. The function `socfpga_sysreset_request()` triggers the warm reset, and upon SPL re-entry, the updated `lowlevel_init_soc64.S` handles the necessary initialization. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee

ddr: altera: agilex: Get ACF from boot scratch register

2025-08-08T14:20:49Z

The DDR data rate must be set correctly in the DDRIOCTRL register according to the Actual Clock Frequency (ACF) value. By enabling the reading of ACF value from bit 18 of the boot scratch register during initialization, the DDR data rate is able to be configured accurately. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee