u-boot.git/arch/arm/mach-tegra/clock.c, branch main

ARM: tegra: clock: take in account PLLD/D2 enable bit on clock_set_rate

2025-04-12T06:42:35Z

PLLD and PLLD2 clocks possess a unique enable bit within their miscellaneous register. Take this into account when using clock_set_rate function. Signed-off-by: Svyatoslav Ryhel

ARM: tegra: clock: fix PLLD/PLLD2 related clock calculations

2025-03-11T15:39:52Z

While PLLD/D2 is the nominal parent clock, all derived clocks are generated from its single output, plld_out0, which is PLLD/D2 divided by two. Direct use of PLLD/D2 is absent in peripheral clock configurations. Therefore, clock derivation formulas must take in account this division. Signed-off-by: Jonas Schwöbel Signed-off-by: Svyatoslav Ryhel

Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"

2024-05-20T19:35:03Z

As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman Signed-off-by: Tom Rini

Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""

2024-05-19T14:16:36Z

When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman Signed-off-by: Tom Rini

arm: tegra: Remove and add needed includes

2024-05-06T21:06:33Z

Remove from all mach-tegra and include/asm/arch-tegra files and when needed add missing include files directly. Signed-off-by: Tom Rini

ARM: tegra30: clock: implement PLLD2 support

2023-12-19T19:24:11Z

PLLD2 is a simple clock (controlled by 2 registers) and appears starting from T30. Primary use of PLLD2 is as main HDMI clock parent. Signed-off-by: Svyatoslav Ryhel

ARM: tegra: clock: support get and set rate for simple PLL

2023-12-19T19:24:11Z

Simple PLL clocks like PLLD2 were omitted since they do not share common 4 register structure with main clocks. Such clocks are containd in simple PLL group. Only clock_start_pll function supported them. This patch expands this support on clock_set_rate and clock_get_rate which should make simple PLL clocks equal to main PLL clocks. Signed-off-by: Svyatoslav Ryhel

ARM: tegra: clock: add clock_decode_pair helper

2023-02-23T19:55:36Z

Get periph clock id and its parent from device tree. This works by looking up the peripheral's 'clocks' node and reading out the second and fourth cells, which are the peripheral and PLL clock numbers. Tested-by: Andreas Westman Dorcsak # ASUS TF T30 Tested-by: Robert Eckelmann # ASUS TF101 T20 Tested-by: Svyatoslav Ryhel # HTC One X Signed-off-by: Svyatoslav Ryhel Signed-off-by: Tom

ARM: tegra: remap clock_osc_freq for all Tegra family

2023-02-02T17:16:41Z

Enum clock_osc_freq was designed to use only with T20. This patch remaps it to use additional frequencies, added in T30+ SoC while maintaining backwards compatibility with T20. Tested-by: Andreas Westman Dorcsak # ASUS TF600T T30 Tested-by: Jonas Schwöbel # Surface RT T30 Tested-by: Robert Eckelmann # ASUS TF101 T20 Tested-by: Agneli # Toshiba AC100 T20 Tested-by: Thierry Reding # T30, T124, T210 Tested-by: Svyatoslav Ryhel # LG P895 T30 Signed-off-by: Svyatoslav Ryhel Reviewed-by: Simon Glass Signed-off-by: Tom

doc: replace @return by Return:

2022-01-19T17:11:34Z

Sphinx expects Return: and not @return to indicate a return value. find . -name '*.c' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; find . -name '*.h' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; Signed-off-by: Heinrich Schuchardt