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<title>u-boot.git/arch/arm/mach-tegra, branch master</title>
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<updated>2026-06-25T00:13:24Z</updated>
<entry>
<title>treewide: move bi_dram[] from bd to gd</title>
<updated>2026-06-25T00:13:24Z</updated>
<author>
<name>Ilias Apalodimas</name>
<email>ilias.apalodimas@linaro.org</email>
</author>
<published>2026-06-17T07:48:19Z</published>
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<id>urn:sha1:1174c99ab421168221be372bd83a4143bf5f167d</id>
<content type='text'>
Currently, the bi_dram[] information is stored in the board info
structure (bd). Because bd is only valid after reserve_board(),
dram_init_banksize() must be called late in the initialization process.
This limitation is problematic, as it forces us to rely on a variety of
bespoke functions to determine board RAM, bank memory sizes, and other
early setup requirements.

By moving bi_dram[] into the global data (gd), we can run it earlier.
This is particularly convenient since boards define their own
dram_init_banksize() routines, which do not always rely on parsing
Device Tree (DT) memory nodes.

Additionally, U-Boot defaults to relocating to the top of the first memory
bank. While boards currently use custom functions to override this
behavior, having the DRAM bank information available earlier in gd makes
relocating to a different bank trivial and standardizes the process.

Reviewed-by: Anshul Dalal &lt;anshuld@ti.com&gt;
Tested-by: Michal Simek &lt;michal.simek@amd.com&gt; # Versal Gen 2 Vek385
Tested-by: Anshul Dalal &lt;anshuld@ti.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Ilias Apalodimas &lt;ilias.apalodimas@linaro.org&gt;
Tested-by: Christophe Leroy (CS GROUP) &lt;chleroy@kernel.org&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: ap: add debug prints for unknown SKU</title>
<updated>2026-03-20T15:41:53Z</updated>
<author>
<name>Ion Agorria</name>
<email>ion@agorria.com</email>
</author>
<published>2026-01-27T09:27:33Z</published>
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<id>urn:sha1:1f32eff8cedc0baf1d595ebf247772bccb950cc7</id>
<content type='text'>
Add debug log prints with a message that SKU is unknown.

Signed-off-by: Ion Agorria &lt;ion@agorria.com&gt;
Signed-off-by: Svyatoslav Ryhel &lt;clamor95@gmail.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: ap: add default fallback for Tegra20 SKU</title>
<updated>2026-03-20T15:41:53Z</updated>
<author>
<name>Ion Agorria</name>
<email>ion@agorria.com</email>
</author>
<published>2026-01-27T09:32:20Z</published>
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<id>urn:sha1:0d26afc4848539fc88fa38f55a15f5d9c1ef9c01</id>
<content type='text'>
Until now all Tegra chips except Tegra20 had a fallback if SKU is not
known. This caused issues previously when certain SKU wasn't known. Add a
fallback for Tegra20 aligning it with other Tegra SoC generations.

Signed-off-by: Ion Agorria &lt;ion@agorria.com&gt;
Signed-off-by: Svyatoslav Ryhel &lt;clamor95@gmail.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: ap: add support T20 A04 SKU id</title>
<updated>2026-03-20T15:41:53Z</updated>
<author>
<name>Ion Agorria</name>
<email>ion@agorria.com</email>
</author>
<published>2026-01-27T09:18:36Z</published>
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<id>urn:sha1:eb1f4fd7190d21d25f7d6130757044ecbc40de3f</id>
<content type='text'>
Add definition for Tegra20 SKU 0x4 / A04 found in Sony Tablet P.

Signed-off-by: Ion Agorria &lt;ion@agorria.com&gt;
Signed-off-by: Svyatoslav Ryhel &lt;clamor95@gmail.com&gt;
</content>
</entry>
<entry>
<title>tegra: pmc: Cleanup headers</title>
<updated>2026-02-17T19:50:22Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2026-02-09T01:30:12Z</published>
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<id>urn:sha1:f025f9de6022167e494a88f22751a329b4ac023a</id>
<content type='text'>
No gd users, so remove DECLARE_GLOBAL_DATA_PTR and the including of
"asm/global_data.h". And include "asm/arch-tegra/tegra.h" to avoid
build error.

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>board: microsoft: add Microsoft Surface 2 support</title>
<updated>2025-08-20T13:22:49Z</updated>
<author>
<name>Jonas Schwöbel</name>
<email>jonasschwoebel@yahoo.de</email>
</author>
<published>2023-12-02T07:19:41Z</published>
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<id>urn:sha1:e69e2dc7f5559cb5fe31dddf4b3f5336c25fa0ac</id>
<content type='text'>
Surface 2 is a Surface-series Windows RT hybrid tablet computer created by
Microsoft. Surface 2 uses a 1.7 GHz quad-core Nvidia Tegra 4 chipset with
2 GB of RAM, features 10.6 inch FullHD ClearType HD screen with 16:9 aspect
ratio and 32/64 GB of internal memory that can be supplemented with a
microSDXC card giving up to 64 GB of additional storage.

Signed-off-by: Jonas Schwöbel &lt;jonasschwoebel@yahoo.de&gt;
Signed-off-by: Svyatoslav Ryhel &lt;clamor95@gmail.com&gt;
</content>
</entry>
<entry>
<title>board: samsung: add Samsung Galaxy R (GT-I9103) and Captivate Glide (SGH-i927) support</title>
<updated>2025-08-01T05:46:53Z</updated>
<author>
<name>Ion Agorria</name>
<email>ion@agorria.com</email>
</author>
<published>2024-12-01T23:24:47Z</published>
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<id>urn:sha1:c55cbaf133b3d31a21b54507d74faeca109b8746</id>
<content type='text'>
The Galaxy R (GT-I9103) and Captivate Glide (SGH-i927) are both Tegra 2
based Samsung smartphones released in 2011. They both feature 1 GB of RAM
and 8 GB of expandable flash memory. The key difference is that the
Captivate Glide has an OLED panel (contrary to LCD in Galaxy R) and a
QWERTY keyboard in form factor of a slider.

Signed-off-by: Ion Agorria &lt;ion@agorria.com&gt;
Reviewed-by: Svyatoslav Ryhel &lt;clamor95@gmail.com&gt;
Signed-off-by: Svyatoslav Ryhel &lt;clamor95@gmail.com&gt;
</content>
</entry>
<entry>
<title>board: chagall: add Pegatron Chagall support</title>
<updated>2025-08-01T05:43:41Z</updated>
<author>
<name>Svyatoslav Ryhel</name>
<email>clamor95@gmail.com</email>
</author>
<published>2025-03-15T13:13:17Z</published>
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<id>urn:sha1:d564f395bcf933d5986723b4a02783338114977c</id>
<content type='text'>
The Pegatron Chagall (originally built by Pegatron, but later rebranded by
other vendors under names Fujitsu Stylistic M532, Olivetti Olipad 3,
Siragon 4N, Realpad Bunaken, DNS AirTab P110w / P110g etc) is a mostly
business-oriented tablet sold in 2012 in different variants, mostly in
Europe, with slight differences in storage size (16GB/32GB) and presence
of built-in cellular modem.

Tested-by: Raffaele Tranquillini &lt;raffaele.tranquillini@gmail.com&gt;
Signed-off-by: Svyatoslav Ryhel &lt;clamor95@gmail.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Use AES engine for crypto functions</title>
<updated>2025-08-01T05:43:41Z</updated>
<author>
<name>Ion Agorria</name>
<email>ion@agorria.com</email>
</author>
<published>2025-06-04T13:31:59Z</published>
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<id>urn:sha1:0106f051d7e1f2a0121876c251d55f812d2b8faa</id>
<content type='text'>
Previously software based AES encryption was used with previously known
device specific keys (SBK), now that we have AES driver we can simply
delegate this to the engine without prior knowledge of the key (assuming
it is still loaded).

Signed-off-by: Ion Agorria &lt;ion@agorria.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Add LP0 support for ODM production</title>
<updated>2025-08-01T05:43:41Z</updated>
<author>
<name>Ion Agorria</name>
<email>ion@agorria.com</email>
</author>
<published>2025-01-07T00:53:19Z</published>
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<id>urn:sha1:f230bc6cf7b1ce24bd1f95d7460965591c5aef37</id>
<content type='text'>
Now that we have working AES engine driver we can request the warmboot code
to be encrypted and signed  with SBK if the device requires so. This
unlocks LP0 support for most devices in the wild as they use ODM Production
Secure.

We are not aware of any "ODM Production Open" device nor have access to
thus this has not been tested on one, merely added for completeness.

Signed-off-by: Ion Agorria &lt;ion@agorria.com&gt;
</content>
</entry>
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