u-boot.git/arch/arm/mach-uniphier/init, branch master

ARM: uniphier: refactor spl_init_board()

2017-01-17T16:22:30Z

Merge init-*.c into a single file using a table of callbacks because the initialization flow is almost common among SoCs. Signed-off-by: Masahiro Yamada

ARM: uniphier: refactor Support Card init code

2017-01-17T00:00:40Z

Splitting reset assertion (support_card_reset) and deassertion (support_card_init) is not adding much value any more. Handle all the initialization of Support Card in support_card_init(), then remove support_card_reset(). Also, detect_num_flash_banks() can have a static qualifier. Signed-off-by: Masahiro Yamada

ARM: uniphier: refactor SBC init code

2017-01-17T00:00:40Z

Merge sbc-admulti.c and sbc-savepin.c into a single file to avoid code duplication. Signed-off-by: Masahiro Yamada

ARM: uniphier: refactor MEMCONF init code

2017-01-17T00:00:40Z

Currently, memconf-sld3.c and memconf-pxs2.c duplicate the code. There are 3 patterns in terms of MEMCONF init: - DRAM 2 channels: LD4, sLD8, Pro4, Pro5, LD11 - DRAM 3 channels: sLD3 - DRAM 3 channels (Ch2 is disable by MEMCONF[21]): Pxs2, LD20 All of them can be moved into a single file by a little more refactoring. Signed-off-by: Masahiro Yamada

ARM: uniphier: split out UMC clock enable

2017-01-17T00:00:40Z

The clock enable bits for UMC are more SoC-specific than for the other hardware blocks. Separate the UMC clocks and the other clocks for better code reuse across SoCs. Signed-off-by: Masahiro Yamada

ARM: uniphier: do not setup pins for System Bus on NAND boot mode

2016-10-10T01:03:23Z

For LD11 and LD20 SoCs, the System Bus and NAND are multiplexed in the same I/O pins. When booting from a NAND device, pin-mux for the System Bus must not be set-up because they are exclusive with each other. Signed-off-by: Masahiro Yamada

ARM: uniphier: add PLL init code for LD11 SoC

2016-09-22T16:00:23Z

- Initialize PLLs (SPL initializes only DPLL to save the precious SPL memory footprint) - Adjust CPLL/MPLL to the final tape-out frequency - Set the Cortex-A53 clock to the maximum frequency since it is running at 500MHz (SPLL/4) on startup Signed-off-by: Masahiro Yamada

ARM: uniphier: add PLL init code for LD20 SoC

2016-09-18T15:12:26Z

Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot proper. Split the common code into pll-base-ld20.c for easier re-use. Signed-off-by: Masahiro Yamada

ARM: uniphier: move PLL init code to U-Boot proper where possible

2016-09-18T15:06:44Z

The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada

ARM: uniphier: consolidate System Bus pin-mux settings for LD11/LD20

2016-09-18T14:47:18Z

Use the pin-mux data in the pinctrl drivers by directly calling pinctrl_generic_set_state(). Signed-off-by: Masahiro Yamada