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<title>u-boot.git/arch/arm/mach-versal-net/include, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
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<updated>2026-07-08T06:55:51Z</updated>
<entry>
<title>arm64: versal-net: Move bootmode decoding out of board code</title>
<updated>2026-07-08T06:55:51Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@amd.com</email>
</author>
<published>2026-06-23T12:53:37Z</published>
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<id>urn:sha1:9048a9c44d5ffc99a38227df4167d401f7129aae</id>
<content type='text'>
versal_net_get_bootmode() open-coded the
IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) selection between the firmware call
zynqmp_pm_get_bootmode_reg() and a direct readl() in board code. Like
the Versal change, move the whole function behind an overridable hook so
generic board code stays free of firmware specifics and is ready for
SCMI.

The weak versal_net_get_bootmode() in arch/arm/mach-versal-net does the
plain MMIO read via versal_net_bootmode_reg() and decodes it (used at EL3
and without firmware). When CONFIG_ZYNQMP_FIRMWARE is enabled,
firmware-zynqmp.c provides a strong definition that reads the register
through the firmware call, falling back to the direct read at EL3 where
the SMC path to firmware is unavailable. This preserves the existing
firmware-based bootmode behaviour while removing the firmware interface
from board code; the now unused zynqmp_firmware.h include is dropped.

Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://patch.msgid.link/be67e9c6d0bc36840a46594413886d2003967c64.1782219202.git.michal.simek@amd.com
</content>
</entry>
<entry>
<title>arm64: versal-net: Move board_early_init_r clock setup to mach code</title>
<updated>2026-07-08T06:55:51Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@amd.com</email>
</author>
<published>2026-06-23T12:53:33Z</published>
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<id>urn:sha1:d885e802ce8722a4dae77255b7aa16ccaf7976d8</id>
<content type='text'>
board_early_init_r() programmed the IOU switch clock and the system
timestamp counter directly with readl()/writel() in board code. This is
SoC register setup rather than board policy, and the same block is
duplicated across the Xilinx SoCs.

Move it into versal_net_timer_setup() in arch/arm/mach-versal-net so the
board hook only keeps the EL3 guard and calls the helper.

Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://patch.msgid.link/10dd9f35d03be0402ce13475f20b2cd3761189a6.1782219202.git.michal.simek@amd.com
</content>
</entry>
<entry>
<title>arm64: versal: Add SelectMAP boot mode identification</title>
<updated>2023-10-09T11:03:23Z</updated>
<author>
<name>Polak, Leszek</name>
<email>LPolak@arri.de</email>
</author>
<published>2023-10-08T14:34:42Z</published>
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<id>urn:sha1:facfa5659b4dfbfffa91283a1234297a744bf28a</id>
<content type='text'>
The SelectMAP configuration interface provides an 8-bit,
16-bit or 32-bit bidirectional data bus interface to the Versal FPGA
configuration logic that can be used for both configuration and readback.

A connected microcontoller to the SelectMAP interface can load boot
image with bitstream, TF-A (ARM Trusted Firmware) and U-Boot.

This commit adds the missing identification of the SelectMAP mode.

Signed-off-by: Polak, Leszek &lt;LPolak@arri.de&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Michal Simek &lt;michal.simek@amd.com&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Link: https://lore.kernel.org/r/DU0PR07MB8419F7765892CDBCE7D559C5C8CFA@DU0PR07MB8419.eurprd07.prod.outlook.com
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
</entry>
<entry>
<title>xilinx: Consolidate zynqmp_mmio_read/write in zynqmp_firmware.h</title>
<updated>2023-07-21T07:00:38Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@amd.com</email>
</author>
<published>2023-06-23T12:51:57Z</published>
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<id>urn:sha1:5b90412cbfcbf7b1df9ed34e0dab255838f43ea5</id>
<content type='text'>
zynqmp_mmio_read/write() are firmware provided hooks that's why use only
zynqmp_firmware.h for function declaration.

Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/e7489556f9e447c737a578c169d7e1e43586a273.1687524706.git.michal.simek@amd.com
</content>
</entry>
<entry>
<title>cadence_qspi: Enable flash reset for Versal NET platform</title>
<updated>2023-07-21T07:00:38Z</updated>
<author>
<name>Ashok Reddy Soma</name>
<email>ashok.reddy.soma@amd.com</email>
</author>
<published>2023-06-14T12:04:52Z</published>
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<id>urn:sha1:34dec6a443df2adb5df2c65b2c441652c5976b44</id>
<content type='text'>
Enable flash reset functionality for Versal NET platform.
In cadence_qspi.c there is weak function defined for reset, hence remove
the check for config, so that it will work for Versal and Versal NET
platforms.

Add register defines in Versal NET hardware.h for mini U-Boot flash
reset.

Add read_delay initialization for Versal NET also.

Signed-off-by: Ashok Reddy Soma &lt;ashok.reddy.soma@amd.com&gt;
Link: https://lore.kernel.org/r/20230614120452.21019-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
</entry>
<entry>
<title>arm64: versal-net: Add support for SPP production version</title>
<updated>2023-06-12T11:24:31Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@amd.com</email>
</author>
<published>2023-05-17T08:21:32Z</published>
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<id>urn:sha1:3e95bf9b76abde1f74b2998cd612cac22b9a1c20</id>
<content type='text'>
Production version restarting platform version field from 0 that's why add
new calculation to be able to use different DT for these platforms.
Requested DT names for production silicons for IPP/SPP and EMU platform are
versal-net-ipp-rev2.0.dts and versal-net-emu-rev2.0.dts.
If platform version increase numbers revision can be even higher.
As of today platform version is 2 that's why expected is rev2.2.

Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/691e166b3cf2643d7edf482bda5500163eecb35a.1684311689.git.michal.simek@amd.com
</content>
</entry>
<entry>
<title>arm64: versal-net: Detect and display bootmode</title>
<updated>2023-06-12T11:24:31Z</updated>
<author>
<name>Ashok Reddy Soma</name>
<email>ashok.reddy.soma@amd.com</email>
</author>
<published>2023-05-16T14:47:53Z</published>
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<id>urn:sha1:ded539ff6633f3ba493e18bf23ce489bfc03f28d</id>
<content type='text'>
Read boodmode register using versal_net_get_bootmode() in board_late_init
and prepare corresponding distro boot command sequence based on it.

versal_net_get_bootmode() will be changed to use smc calls later, but
for now directly reads the register.

Signed-off-by: Ashok Reddy Soma &lt;ashok.reddy.soma@amd.com&gt;
Link: https://lore.kernel.org/r/20230516144753.30869-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
</entry>
<entry>
<title>xilinx: zynqmp: Add missing prototype for zynqmp_mmio_write</title>
<updated>2023-03-09T12:15:00Z</updated>
<author>
<name>Algapally Santosh Sagar</name>
<email>santoshsagar.algapally@amd.com</email>
</author>
<published>2023-03-01T10:33:33Z</published>
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<id>urn:sha1:cc24fd78593896ba038c71eb356b32fdaa1cd690</id>
<content type='text'>
Add missing prototype to fix the sparse warning, warning: no
previous prototype for 'zynqmp_mmio_write' [-Wmissing-prototypes].

Signed-off-by: Algapally Santosh Sagar &lt;santoshsagar.algapally@amd.com&gt;
Signed-off-by: Ashok Reddy Soma &lt;ashok.reddy.soma@amd.com&gt;
Link: https://lore.kernel.org/r/20230301103334.1455-2-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
</entry>
<entry>
<title>xilinx: versal-net: Add support for timer and start it</title>
<updated>2023-01-16T14:34:37Z</updated>
<author>
<name>Ashok Reddy Soma</name>
<email>ashok.reddy.soma@amd.com</email>
</author>
<published>2023-01-10T07:44:07Z</published>
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<id>urn:sha1:724379d9afc850de2767094987a761f096af7718</id>
<content type='text'>
Add support for starting timer by setting up time stamp generator
registers. This is done only for EL3 i.e. mini U-Boot case.
For other cases, it will be done TF-A.

Add COUNTER_FREQUENCY and IOU_SWITCH_DIVISOR0 to Kconfig so that they
can be tuned as required.

Signed-off-by: Ashok Reddy Soma &lt;ashok.reddy.soma@amd.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/fcd8b0dc4b45a11f5e753afff42f84738ac813da.1673336645.git.michal.simek@amd.com
</content>
</entry>
<entry>
<title>spi: cadence_qspi: Add support for Versal NET platform</title>
<updated>2022-09-26T12:23:29Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@amd.com</email>
</author>
<published>2022-09-19T12:21:03Z</published>
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<id>urn:sha1:1e681448a38dcaf95a58592410382c3324c2cc00</id>
<content type='text'>
Trivial changes to support cadence ospi driver for Versal NET platform.
Also avoid ospi flash reset for now.

Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/0789141f432189aab69bc496fe33e0218d1d7510.1663589964.git.michal.simek@amd.com
</content>
</entry>
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