u-boot.git/arch/arm/mach-versal2/include, branch master Unnamed repository; edit this file 'description' to name the repository. arm64: versal2: Populate DRAM banks before page table size calculation 2026-02-13T07:16:24+00:00 Pranav Sanwal pranav.sanwal@amd.com 2026-01-29T12:00:21+00:00 3aebac5a759b02d5ac5c893770bc45d3b8932d62 Move DRAM bank detection from fdtdec to custom implementation to ensure memory banks are populated before get_page_table_size() is called during MMU initialization. The current fdtdec-based approach populates gd->bd->bi_dram[] too late in the boot sequence, causing get_page_table_size() to be called with unpopulated DRAM information. This prevents dynamic page table sizing based on actual memory configuration. Parse /memory nodes in dram_init() to fill versal2_mem_map[] early enough for MMU setup. Supports up to CONFIG_NR_DRAM_BANKS (36) non-contiguous banks with high memory regions (>4GB) and use __weak get_page_table_size implementation to estimate page table size based on the populated DRAM banks. Signed-off-by: Pranav Sanwal <pranav.sanwal@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20260129120021.1328653-3-pranav.sanwal@amd.com 
Move DRAM bank detection from fdtdec to custom implementation to
ensure memory banks are populated before get_page_table_size() is
called during MMU initialization.

The current fdtdec-based approach populates gd->bd->bi_dram[] too
late in the boot sequence, causing get_page_table_size() to be
called with unpopulated DRAM information. This prevents dynamic
page table sizing based on actual memory configuration.

Parse /memory nodes in dram_init() to fill versal2_mem_map[]
early enough for MMU setup. Supports up to
CONFIG_NR_DRAM_BANKS (36) non-contiguous banks with high memory
regions (>4GB) and use __weak get_page_table_size implementation
to estimate page table size based on the populated DRAM banks.

Signed-off-by: Pranav Sanwal <pranav.sanwal@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20260129120021.1328653-3-pranav.sanwal@amd.com
arm64: versal2: Read and show multiboot value 2025-12-19T07:25:27+00:00 Michal Simek michal.simek@amd.com 2025-11-27T08:28:46+00:00 29427fdf7198953f361ce6535b67272e3645d53b SOC can boot from different boot medias and also different offsets that's why by default show multiboot value to be aware which image system is booting out of. It is especially useful for systems with A/B update enabled. Also limit zynqmp_pm_get_pmc_multi_boot_reg() usage only for Versal and Versal Gen 2. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/fd7564ce2f51d965c273e939e98de01beb92e6f5.1764232124.git.michal.simek@amd.com 
SOC can boot from different boot medias and also different offsets that's
why by default show multiboot value to be aware which image system is
booting out of. It is especially useful for systems with A/B update
enabled.
Also limit zynqmp_pm_get_pmc_multi_boot_reg() usage only for Versal and
Versal Gen 2.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/fd7564ce2f51d965c273e939e98de01beb92e6f5.1764232124.git.michal.simek@amd.com
ufs: amd-versal2: Use raw read/write for SLCR/CACHE registers 2025-04-16T11:42:06+00:00 Venkatesh Yadav Abbarapu venkatesh.abbarapu@amd.com 2025-03-20T09:13:24+00:00 5b8d6dcf7ce1b9629cec02e8d17db530776de5b4 Update the firmware driver UFS APIs zynqmp_pm_ufs_* to directly read/write to the pmc_iou_slcr and efuse_cache registers. Replace these raw reads/writes with the xilinx_pm_request() API with the correct arguments once the PM related changes are done. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/ee2d1ad2e07e96f1948ab6ffe8f3c50a3b8f9be9.1742462001.git.michal.simek@amd.com 
Update the firmware driver UFS APIs zynqmp_pm_ufs_* to directly
read/write to the pmc_iou_slcr and efuse_cache registers. Replace
these raw reads/writes with the xilinx_pm_request() API with the
correct arguments once the PM related changes are done.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ee2d1ad2e07e96f1948ab6ffe8f3c50a3b8f9be9.1742462001.git.michal.simek@amd.com
amd: versal2: Add the UFS boot mode support 2025-04-16T11:42:06+00:00 Venkatesh Yadav Abbarapu venkatesh.abbarapu@amd.com 2025-02-25T03:28:06+00:00 253da1f0a2821bf741c8dc24ed2e568b7013f6e0 Add the UFS boot mode support and update the boot_targets with ufs mode. If the UFS device is not accessible from APU and running this is detected as a warning, as the device is not accessible. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20250225032806.1842581-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com> 
Add the UFS boot mode support and update the boot_targets with
ufs mode. If the UFS device is not accessible from APU and
running this is detected as a warning, as the device is not
accessible.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250225032806.1842581-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
arm64: versal2: Show major and minor silicon version 2025-03-03T15:09:59+00:00 Michal Simek michal.simek@amd.com 2025-02-18T12:43:07+00:00 f92623704e58e80814c087a10d0ee385221df20b ES1 silicon is 0x10 (16) and production is 0x20 (32) but correct number to see are v1.0 or v2.0 instead of v16 or v32. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20095339334fe07f373ffae3bdbfec51f5a00dc7.1739882585.git.michal.simek@amd.com 
ES1 silicon is 0x10 (16) and production is 0x20 (32) but correct number to
see are v1.0 or v2.0 instead of v16 or v32.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20095339334fe07f373ffae3bdbfec51f5a00dc7.1739882585.git.michal.simek@amd.com
arm64: versal2: Add support for AMD Versal Gen 2 2024-06-17T14:02:29+00:00 Michal Simek michal.simek@amd.com 2024-05-29T14:47:58+00:00 40f5046c221a7b2719c49b51acefe12914b213e5 Add support for AMD Versal Gen 2. SoC is based on Cortex-a78ae 4 cluster/2 cpu core each. A lot of IPs are shared with previous families. There are couple of new IP blocks where the most interesting from user point of view is UFS. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/bc2b70831ce1031bd0fac32357bff84936e1310f.1716994063.git.michal.simek@amd.com 
Add support for AMD Versal Gen 2. SoC is based on Cortex-a78ae 4 cluster/2
cpu core each. A lot of IPs are shared with previous families. There are
couple of new IP blocks where the most interesting from user point of view
is UFS.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/bc2b70831ce1031bd0fac32357bff84936e1310f.1716994063.git.michal.simek@amd.com