u-boot.git/arch/arm, branch master

stm32mp2: update part number for STM32MP251/3

2026-05-26T11:46:30+00:00

update part number for STM32MP251/3 for last cut revision.

Signed-off-by: Patrice Chotard 
Reviewed-by: Patrick Delaunay

ARM: dts: stm32: enable SMC watchdog for STM32MP15 SCMI config

2026-05-26T11:46:30+00:00

For this configuration, the watchdog (iwdg1) is secured and managed by
OP-TEE. Add an watchdog node with arm,smc-wdt compatible, and disable
iwdg2 node which is then no more used.

Signed-off-by: Yann Gautier 
Reviewed-by: Patrice Chotard

Merge patch series "Fix speculative access to firewalled regions on AM62 SoCs"

2026-05-25T15:29:54+00:00

Anshul Dalal  says:

This patch series fixes firewall exceptions observed on AM62 family of
devices due to speculative accesses made by the A53 core to secure DDR
regions.

Link: https://lore.kernel.org/r/20260520-am62_firewall_exception_fix-v3-0-9ca3dc40aea4@ti.com

mach-k3: enable mmu after reserved memory is unmapped

2026-05-25T15:29:50+00:00

Currently the sequence to enable caches for the A53/A72 core on K3
devices looks as follows:

 1. Map entire DDR banks
 2. Setup page tables (done by mmu_setup)
 3. Enable MMU
 4. Unmap reserved-memory regions
 5. Enable caches

However there is a brief period of execution between #3 and #4 where the
core can issue speculative accesses to the entire DDR space (including
the reserved-memory regions) despite the caches being disabled.

A firewall exception is triggered whenever such speculative access is
made to secure DDR region of TFA or OP-TEE. This patch fixes the issue
by re-ordering the sequence as follows:

 1. Map entire DDR banks
 2. Setup page tables
 3. Unmap reserved-memory regions
 4. Enable MMU
 5. Enable caches

Fixes: f1c694b8fdde ("mach-k3: map all banks using mem_map_from_dram_banks")
Reported-by: Suhaas Joshi 
Signed-off-by: Anshul Dalal 
Reviewed-by: Ilias Apalodimas

arm: armv8: mmu: move mmu enablement out of mmu_setup

2026-05-25T15:29:50+00:00

Currently mmu_setup for ARMv8 performs two functions, first it sets up
the page tables based the memory map provided by the board and then it
enables the MMU.

However for some platforms runtime fixes to the generated page tables
are required before the MMU can be enabled, such as K3 family of SoCs.

Therefore this patch moves the enablement of the MMU out of mmu_setup
and to a standalone mmu_enable function to give more granular control to
the platforms.

Note that no functional changes are intended from this patch.

Reviewed-by: Ilias Apalodimas 
Signed-off-by: Anshul Dalal

arm: renesas: Add Renesas R-Car R8A78000 X5H Cortex-M33 RSIP port

2026-05-21T19:48:05+00:00

Add support for building U-Boot for Cortex-M33 RSIP core in Renesas
R-Car Gen5 R8A78000 X5H SoC. The main goal is to start U-Boot on the
Cortex-M33 RSIP core, which initializes the hardware and then starts
the Cortex-M33 SCP and Cortex-A720 cores which run the SCP firmware
and applications software respectively. The SCP is responsible for
platform resource management, and is used to start other CPU cores.

The Cortex-M33 build contains its own r8a78000_ironhide_cm33_defconfig
which configures the build for aarch32 instruction set compatible with
the ARMv8M core. The build also uses -cm33 DT and -u-boot.dtsi which
are derived from their non-CM33 counterparts, and add CM33 specifics.

The arch/arm/mach-renesas/u-boot-rsip.lds is derived from generic
arch/arm/cpu/u-boot.lds with adjustments to cater to the RSIP core,
those are entrypoint before vectors, __data_start/__data_end symbols
for data-only relocation, and placement of BSS into read-write SRAM
area.

Signed-off-by: Marek Vasut

arm: renesas: Generate u-boot-elf.shdr for R-Car Gen5 RSIP

2026-05-21T19:48:05+00:00

Add target to generate u-boot-elf.shdr for R-Car Gen5 Cortex-M33
RSIP core. The resulting .shdr SREC file can be written into the
HF at offset 0.

Signed-off-by: Marek Vasut

arm: renesas: Generate u-boot-elf.scif for R-Car Gen5 RSIP

2026-05-21T19:48:05+00:00

Add target to generate u-boot-elf.scif for R-Car Gen5 Cortex-M33
RSIP core. The resulting .scif SREC file can be loaded using the
SCIF loader to start U-Boot on the RSIP core.

Signed-off-by: Marek Vasut

arm64: dts: renesas: Switch to remap drivers on R-Car Gen5 R8A78000 X5H

2026-05-21T19:48:05+00:00

Point every direct user of SCMI clock protocol at CPG node instead
of SCMI clock protocol node. Point every direct user of SCMI reset
and power domain protocol at a matching newly introduced MDLC node
instead of the SCMI reset and power domain protocol nodes.

This allows the CPG and MDLC remap drivers bound to CPG node and MDLC
nodes to remap between DT clock, reset and power domain IDs and SCMI
clock, reset and power domain IDs. This makes U-Boot on R-Car X5H
compatible with multiple SCP firmware versions. Currently supported
versions of SCP firmware are 4.28, 4.31 and 4.32.

Signed-off-by: Marek Vasut

arm64: renesas: Select R-Car Gen5 R8A78000 X5H MDLC power domain and reset driver

2026-05-21T19:48:05+00:00

Select the R8A78000 power domain and reset driver on R-Car Gen5 X5H
SoC by default. The power domain and reset driver is used to remap
DT power domain and reset IDs to SCMI power domain and reset IDs,
which is necessary to support multiple SCP firmware versions with
varying SCMI clock IDs across versions.

Signed-off-by: Marek Vasut