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<title>u-boot.git/arch/arm, branch v2013.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm?h=v2013.04</id>
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<updated>2013-04-17T01:00:40Z</updated>
<entry>
<title>exynos: Correct use of 64-bit division</title>
<updated>2013-04-17T01:00:40Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2013-04-13T04:26:41Z</published>
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<id>urn:sha1:dc47e2bc7d1c5307b18b9a43f3286969e36a974e</id>
<content type='text'>
The current code is causing errors like this on my toolchains:

/usr/x86_64-pc-linux-gnu/armv7a-cros-linux-gnueabi/binutils-bin/2.22/
ld.bfd.real: failed to merge target specific data of file /usr/lib/gcc/
armv7a-cros-linux-gnueabi/4.7.x-google/libgcc.a(_divdi3.o)

Use do_div() to avoid this.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</content>
</entry>
<entry>
<title>Tegra: Split tegra_get_chip_type() into soc &amp; sku funcs</title>
<updated>2013-04-15T18:01:38Z</updated>
<author>
<name>Tom Warren</name>
<email>twarren@nvidia.com</email>
</author>
<published>2013-04-10T17:32:32Z</published>
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<id>urn:sha1:49493cb7144f0c51a5aaecc75fcd1b3f157633ba</id>
<content type='text'>
As suggested by Stephen Warren, use tegra_get_chip() to return
the pure CHIPID for a Tegra SoC (i.e. 0x20 for Tegra20, 0x30 for
Tegra30, etc.) and rename tegra_get_chip_type() to reflect its true
function, i.e. tegra_get_chip_sku(), which returns an ID like
TEGRA_SOC_T25, TEGRA_SOC_T33, etc.

Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
Reviewed-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>Tegra: Fix MSELECT clock divisors for T30/T114.</title>
<updated>2013-04-15T18:01:38Z</updated>
<author>
<name>Tom Warren</name>
<email>twarren@nvidia.com</email>
</author>
<published>2013-04-03T21:39:30Z</published>
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<id>urn:sha1:d94c2dbd0a55d742ab6ed9bd0c51b27ceed4084e</id>
<content type='text'>
A comparison of registers between our internal NV U-Boot and
u-boot-tegra/next showed some discrepancies in the MSELECT
clock divisor programming. T20 doesn't have a MSELECT clk src reg.

Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
Reviewed-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>Tegra114: Initialize System Counter (TSC) with osc frequency</title>
<updated>2013-04-15T18:01:38Z</updated>
<author>
<name>Tom Warren</name>
<email>twarren@nvidia.com</email>
</author>
<published>2013-04-01T22:48:54Z</published>
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<id>urn:sha1:b40f734af9fdc47a0993f1f94f32d40a86f30587</id>
<content type='text'>
T114 needs the SYSCTR0 counter initialized so the TSC can be
read by the kernel. Do it in the bootloader since it's a write-once
deal (secure/non-secure mode dependent).

Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
Reviewed-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>Tegra: Configure L2 cache control reg properly.</title>
<updated>2013-04-15T18:01:38Z</updated>
<author>
<name>Tom Warren</name>
<email>twarren@nvidia.com</email>
</author>
<published>2013-03-25T23:22:26Z</published>
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<id>urn:sha1:d0edce4fa394325a0ccfd38a5d668fb5ee1af34d</id>
<content type='text'>
Without this change, kernel fails at calling function cache_clean_flush
during kernel early boot.

Aprocryphally, intended for T114 only, so I check for a T114 SoC.
Works (i.e. dalmore 3.8 kernel now starts printing to console).

Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>Tegra: Restore cp15 VBAR _start vector write for ARMv7</title>
<updated>2013-04-15T18:01:37Z</updated>
<author>
<name>Tom Warren</name>
<email>twarren@nvidia.com</email>
</author>
<published>2013-03-28T17:03:22Z</published>
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<id>urn:sha1:3ebbbfe4c78089db47599fc7b57ad016e247dd52</id>
<content type='text'>
A start vector fix was added by AneeshV for OMAP4 (commit 0d479b53),
and caused the old monilithic Tegra builds to hang due to an undefined
instruction trap. Previously, the code needed to run on both the
AVP (ARM7TDI) and A9, and the AVP doesn't have a CP15 register.
I corrected this in commit 6d6c0bae w/#ifndef CONFIG_TEGRA, but
now that we use SPL, and boot the AVP w/o any ARMv7 code, I can
revert my change, and make Aneesh's change apply to Tegra.

Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: support T33 SKU of Tegra30</title>
<updated>2013-04-15T18:01:37Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2013-03-27T09:37:02Z</published>
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<id>urn:sha1:eb222d1d7de5946501ed15c49f9d23bc05fc5a87</id>
<content type='text'>
Make U-Boot aware of the T33 SKU of Tegra30, and treat it identically
to any other Tegra30.

An alternative would be to simply remove the SKU checking from
tegra_get_chip_type(); most use of the value most likely simply wants
to know the current chip, not the specific SKU. Or, the function could
be split into separate tegra_get_chip() and tegra_get_sku() for the
cases where differentiation really is required.

I wonder whether tegra_get_chip_type() should printf() whenever any
unkown chip/SKU is found, although perhaps the function is called so
early that the printf() wouldn't actually make it to the UART anyway.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>ARMv7: start.S: stay in HYP mode if u-boot is entered in it</title>
<updated>2013-04-15T16:30:59Z</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@linaro.org</email>
</author>
<published>2013-04-02T05:43:36Z</published>
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<id>urn:sha1:c4a4e2e20ca226948b62ed116df98f7a3932f2ac</id>
<content type='text'>
The KVM and Xen hypervisors for the Cortex-A15 virtualization
implementation need to be entered in HYP mode. Should the primary
board firmware already enter HYP mode (Calxeda firmware does that),
we should not deliberately drop back to SVC mode.
Since U-boot does not use the MMU, running in HYP mode is just fine.

Signed-off-by: Andre Przywara &lt;andre.przywara@linaro.org&gt;
</content>
</entry>
<entry>
<title>ARM: fix CONFIG_SPL_MAX_SIZE semantics</title>
<updated>2013-04-14T14:07:14Z</updated>
<author>
<name>Albert ARIBAUD</name>
<email>albert.u.boot@aribaud.net</email>
</author>
<published>2013-04-12T05:14:30Z</published>
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<id>urn:sha1:6ebc346111b30f854ead1c06a0afb37f8c704ce4</id>
<content type='text'>
Remove SPL-related ASSERT() in arch/arm/cpu/u-boot.lds
as this file is never used for SPL builds.

Rewrite the ASSERT() in arch/arm/cpu/u-boot-spl.lds
to separately test image (text,data,rodata...) size,
BSS size, and full footprint each against its own max,
and make Tegra boards check full footprint.

Also, output section mmutable is not used in SPL builds.
Remove it.

Finally, update README regarding the (now homogeneous)
semantics of CONFIG_SPL_[BSS_]MAX_SIZE and add the new
CONFIG_SPL_MAX_FOOTPRINT macro.

Signed-off-by: Albert ARIBAUD &lt;albert.u.boot@aribaud.net&gt;
Reported-by: Benoît Thébaudeau &lt;benoit.thebaudeau@advansee.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'</title>
<updated>2013-04-14T08:38:37Z</updated>
<author>
<name>Albert ARIBAUD</name>
<email>albert.u.boot@aribaud.net</email>
</author>
<published>2013-04-14T08:38:37Z</published>
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<id>urn:sha1:8dc16cf9dd6196d99969d12741df186a61a2f9a3</id>
<content type='text'>
</content>
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