u-boot.git/arch/arm, branch v2015.10

Merge branch 'master' of git://git.denx.de/u-boot-arm

2015-10-19T15:30:38Z

ARM: rpi: add another revision of Raspberry Pi A+

2015-10-19T06:12:25Z

Seen this one in the wild. Is labelled "Raspberry Pi Model A+ V1.1, (C) Raspberry Pi 2014". A standard A+ board, much like the one with version 0x12, didn't notice any differencies. Signed-off-by: Lubomir Rintel

ARM: k2e/l: Apply WA for selecting PA clock source

2015-10-18T00:16:13Z

On keystone2 Lamarr and Edison platforms, the PA clocksource mux in PLL REG1, can be changed only after enabling its clock domain. So selecting the output of PASS PLL as input to PA only after enabling the clockdomain. This is as per the debug done by "Vitaly Andrianov " and based on the previous work done by "Hao Zhang " Fixes: d634a0775bcf ("ARM: keystone2: Cleanup PLL init code") Reported-by: Vitaly Andrianov Tested-by: Vitaly Andrianov Signed-off-by: Lokesh Vutla

Merge git://git.denx.de/u-boot-socfpga

2015-10-17T00:21:04Z

arm: dts: socfpga: add "u-boot,dm-pre-reloc" to socfpga_cyclone5_socdk dts

2015-10-16T23:47:31Z

We need "u-boot,dm-pre-reloc" in the socfpga_cyclone5_socdk.dts file in order for the SPL to use SD/MMC. Signed-off-by: Dinh Nguyen

arm: socfpga: enable data/inst prefetch and shared override in the L2

2015-10-16T23:47:31Z

Update the L2 AUX CTRL settings for the SoCFPGA. Enabling D and I prefetch bits helps improve SDRAM performance on the platform. Also, we need to enable bit 22 of the L2. By not having bit 22 set in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. Signed-off-by: Dinh Nguyen

arm: mmu: Add missing volatile for reading SCTLR register

2015-10-16T05:55:51Z

Add 'volatile' qualifier to the asm statement in get_cr() so that the statement is not optimized out by the compiler. (http://comments.gmane.org/gmane.linux.linaro.toolchain/5163) Without the 'volatile', get_cr() returns a wrong value which prevents enabling the MMU and later causes a PCIE VA access failure. Signed-off-by: Alison Wang

Merge branch 'master' of git://git.denx.de/u-boot-arm

2015-10-15T21:45:39Z

pci: pcie_imx: Fix hang on mx6qp

2015-10-15T13:05:13Z

PCI driver currently hangs on mx6qp. Toggle the reset bit with the appropriate timings to fix the issue. Based on the FSL kernel driver implementation. Signed-off-by: Fabio Estevam Acked-by: Stefano Babic

armv8/gic: Fix GIC v2 initialization

2015-10-15T12:47:03Z

Initialize all GICD_IGROUPRn registers and set up GICC_CTLR to enable interrupts to the primary CPU. This fixes issues seen after booting a Linux kernel from U-Boot. Suggested-by: Marc Zyngier Suggested-by: Mark Rutland Cc: Albert Aribaud Cc: Mark Rutland Cc: Marc Zyngier Signed-off-by: Thierry Reding