u-boot.git/arch/arm, branch v2018.07

Merge branch 'master' of git://git.denx.de/u-boot-sunxi

2018-07-04T03:09:34Z

arm: timer: sunxi: add Allwinner timer erratum workaround

2018-07-03T16:30:00Z

The Allwinner A64 SoCs suffers from an arch timer implementation erratum, where sometimes the lower 11 bits of the counter value erroneously become all 0's or all 1's [1]. This leads to sudden jumps, both forwards and backwards, with the latter one often showing weird behaviour. Port the workaround proposed for Linux to U-Boot and activate it for all A64 boards. This fixes crashes when accessing MMC devices (SD cards), caused by a recent change to actually use the counter value for timeout checks. Fixes: 5ff8e54888e4d26a352453564f7f599d29696dc9 ("sunxi: improve throughput in the sunxi_mmc driver") [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2018-May/576886.html Signed-off-by: Andre Przywara Reviewed-by: Philipp Tomsich Tested-by: Jagan Teki Tested-by: Andreas Färber Tested-by: Guillaume Gardet

arm: timer: factor out FSL arch timer erratum workaround

2018-07-03T16:29:46Z

At the moment we have the workaround for the Freescale arch timer erratum A-008585 merged into the generic timer_read_counter() routine. Split those two up, so that we can add other errata workaround more easily. Also add an explaining comment on the way. Signed-off-by: Andre Przywara Tested-by: Jagan Teki Tested-by: Andreas Färber Tested-by: Guillaume Gardet

board/aries: Remove

2018-07-02T19:52:50Z

The various Aries Embedded boards have been orphaned for a year and no one has come forward to take care of them. Remove. Signed-off-by: Tom Rini

Merge branch 'master' of git://git.denx.de/u-boot-usb

2018-06-30T12:52:06Z

mx5: Select ARM_CORTEX_A8_CVE_2017_5715

2018-06-30T12:49:55Z

On a 4.18-rc1 kernel the following warning is seen on i.MX51 and i.MX53: CPU0: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable Select the ARM_CORTEX_A8_CVE_2017_5715 workaround for i.MX51/i.MX53 to fix the problem. With this patch applied the kernel reports: CPU0: Spectre v2: using BPIALL workaround Signed-off-by: Fabio Estevam

ARM: mach-omap2: omap3/am335x: Enable ACR::IBE on Cortex-A8 SoCs for CVE-2017-5715

2018-06-29T15:30:39Z

Enable CVE-2017-5715 option to set the IBE bit. This enables kernel workarounds necessary for the said CVE. With this enabled, Linux reports: CPU0: Spectre v2: using BPIALL workaround This workaround may need to be re-applied in OS environment around low power transition resume states where context of ACR would be lost (off-mode etc). Signed-off-by: Nishanth Menon

ARM: mach-omap2: omap5/dra7: Enable ACTLR[0] (Enable invalidates of BTB) to facilitate CVE_2017-5715 WA in OS

2018-06-29T15:30:39Z

Enable CVE_2017_5715 and since we have our own v7_arch_cp15_set_acr function to setup the bits, we are able to override the settings. Without this enabled, Linux kernel reports: CPU0: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable With this enabled, Linux kernel reports: CPU0: Spectre v2: using ICIALLU workaround NOTE: This by itself does not enable the workaround for CPU1 (on OMAP5 and DRA72/AM572 SoCs) and may require additional kernel patches. Signed-off-by: Nishanth Menon

ARM: Introduce ability to enable invalidate of BTB with ICIALLU on Cortex-A15 for CVE-2017-5715

2018-06-29T15:30:39Z

As recommended by Arm in [1], ACTLR[0] (Enable invalidates of BTB) needs to be set[2] for BTB to be invalidated on ICIALLU. This needs to be done unconditionally for Cortex-A15 processors. Provide a config option for platforms to enable this option based on impact analysis for products. NOTE: This patch in itself is NOT the final solution, this requires: a) Implementation of v7_arch_cp15_set_acr on SoCs which may not provide direct access to ACR register. b) Operating Systems such as Linux to provide adequate workaround in the right locations. c) This workaround applies to only the boot processor. It is important to apply workaround as necessary (context-save-restore) around low power context loss OR additional processors as necessary in either firmware support OR elsewhere in OS. [1] https://developer.arm.com/support/security-update [2] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438c/BABGHIBG.html Cc: Marc Zyngier Cc: Russell King Cc: Tony Lindgren Cc: Robin Murphy Cc: Florian Fainelli Cc: Catalin Marinas Cc: Will Deacon Cc: Christoffer Dall Cc: Andre Przywara Cc: Ard Biesheuvel Cc: Tom Rini Cc: Michael Nazzareno Trimarchi Signed-off-by: Nishanth Menon Tested-by: Fabio Estevam

ARM: Introduce ability to enable ACR::IBE on Cortex-A8 for CVE-2017-5715

2018-06-29T15:30:39Z

As recommended by Arm in [1], IBE[2] has to be enabled unconditionally for BPIALL to be functional on Cortex-A8 processors. Provide a config option for platforms to enable this option based on impact analysis for products. NOTE: This patch in itself is NOT the final solution, this requires: a) Implementation of v7_arch_cp15_set_acr on SoCs which may not provide direct access to ACR register. b) Operating Systems such as Linux to provide adequate workaround in the right locations. c) This workaround applies to only the boot processor. It is important to apply workaround as necessary (context-save-restore) around low power context loss OR additional processors as necessary in either firmware support OR elsewhere in OS. [1] https://developer.arm.com/support/security-update [2] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0344k/Bgbffjhh.html Cc: Marc Zyngier Cc: Russell King Cc: Tony Lindgren Cc: Robin Murphy Cc: Florian Fainelli Cc: Catalin Marinas Cc: Will Deacon Cc: Christoffer Dall Cc: Andre Przywara Cc: Ard Biesheuvel Cc: Tom Rini Cc: Michael Nazzareno Trimarchi Signed-off-by: Nishanth Menon Tested-by: Fabio Estevam