The make macro to check if the binary exceeds the board size limit is taken straight from the root Makefile. Without this and e.g. enabled EFI Vybrid fails booting as the regular size limit check does not take the final u-boot.imx binary size into account which is bigger due to alignment as well as IMX header stuff. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
If the function gpr_init is used in a common MX6 spl implementation we have to ensure that it is only called for suitable cpu types, otherwise it breaks hardware parts like enet1, can1, can2, etc. Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.de>
Fix coverity issues for i.MX8
The new board version has the 2nd FPGA connected via CS# 0 instead of 2 on SPI bus 1. Change this setup in the DT accordingly. Please note that this change does still work on the old board version because the CS signal is not used on this board. Signed-off-by: Stefan Roese <sr@denx.de>
Add the "spi-flash" compatible string so that the generic sf_probe driver can probe the SPI flash on the theadorable Armada-XP board. Signed-off-by: Stefan Roese <sr@denx.de>
With patch 49b23e035d96 (pci: mvebu: Increase size of PCIe default mapping) the mapping size for each PCI(e) controller was increased from 32MiB to 128MiB. This leads to problems on boards with multiple PCIe slots / ports which are unable to map all PCIe ports, e.g. the Armada-XP theadorable: DRAM: 2 GiB (667 MHz, 64-bit, ECC not enabled) SF: Detected m25p128 with page size 256 Bytes, erase size 256 KiB, total 16 MiB Cannot add window '4:f8', conflicts with another window PCIe unable to add mbus window for mem at f0000000+08000000 Model: Marvell Armada XP theadorable This patch moves the base address for the PCI(e) memory spaces from 0xe8000000 to the end of SDRAM (clipped to a max of 0xc0000000 right now). This gives move room and flexibility for PCI(e) mappings. Signed-off-by: Stefan Roese <sr@denx.de> Cc: VlaoMao <vlaomao@gmail.com> Tested-by: VlaoMao <vlaomao at gmail.com>
Commit 3c28576bb0f0 ("arm: dts: imx8qxp: fix build warining")
fixed the dts warning by removing the unnecessary
#address-cells/#size-cells, but the recommendation for regulators is not
to place them under "simple-bus", so move the reg_usdhc2_vmmc regulator
accordingly.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Patch "ARM: rmobile: Mark 4-64GiB as DRAM on Gen3" marked the entire
64bit DRAM space as cachable. On CortexA57, this might result in odd
side effects, where the CPU tries to prefetch from those areas and if
there is no DRAM backing them, CPU bus hang can happen.
This patch fixes it by generating the mem_map structure based on the
actual memory layout obtained from the DT, thus not marking areas
without any DRAM behind them as cachable.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Fixes: c1ec34763811d ("ARM: rmobile: Mark 4-64GiB as DRAM on Gen3")
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Using imply for SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION instead of select ensures we can build without partition support (used to build a network boot only version of SPL and U-Boot). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>