u-boot.git/arch/arm, branch v2020.07

Merge tag 'u-boot-rockchip-20200628' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip

2020-06-28T14:12:07Z

- rk3188 cpu init and APLL fix; - rk3399: Add BOOTENV_SF command; - rk3288 correct vop0 vop1 setting;

rockchip: rk3188: Fix back to BROM boot

2020-06-27T14:12:34Z

Move the setting for noc remap out of SPL code. Changing noc remap inside SPL results in breaking back to BROM boot. Fixes commit c14fe2a8e192 ("rockchip: rk3188: Move SoC one time setting into arch_cpu_init()"). Signed-off-by: Alexander Kochetkov Reviewed-by: Kever Yang

arm: socfpga: misc_s10: Fix EMAC register address calculation

2020-06-26T03:30:24Z

Fix EMAC register address calculation, address need to multiply with sizeof(u32) or 4. This fixes write to invalid address. Signed-off-by: Ley Foon Tan

ARM: dts: imx6q-tbs2910: Fix Ethernet regression

2020-06-25T14:39:48Z

Since commit: commit 6333cbb3817ed551cd7d4e92f7359c73ccc567fc Author: Michael Walle Date: Thu May 7 00:11:58 2020 +0200 phy: atheros: ar8035: remove static clock config We can configure the clock output in the device tree. Disable the hardcoded one in here. This is highly board-specific and should have never been enabled in the PHY driver. If bisecting shows that this commit breaks your board it probably depends on the clock output of your Atheros AR8035 PHY. Please have a look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set "clk-out-frequency = <125000000>" because that value was the hardcoded value until this commit. Signed-off-by: Michael Walle Acked-by: Joe Hershberger , the clock output setting for the AR803x driver is removed from being hardcoded in the PHY driver and should be passed via device tree instead. Update the device tree with the "qca,clk-out-frequency" property so that Ethernet can work again. Reported-by: Soeren Moch Signed-off-by: Fabio Estevam Tested-by: Soeren Moch

mx6cuboxi: enable MMC and eMMC in DT for SPL

2020-06-22T22:08:53Z

Signed-off-by: Walter Lozano

arm: dts: imx: fsl-imx8qm.dtsi: fix gpio aliases

2020-06-22T22:08:53Z

Current aliases missed gpio0 node, and this node shoud be aliased to gpio index 0 to align with i.MX8QXP. Otherwise, we will get below message when running "gpio status" command, and see the reason by "dm uclass". => gpio status Device 'gpio@5d090000': seq 0 is in use by 'gpio@5d080000' Device 'gpio@5d0a0000': seq 1 is in use by 'gpio@5d090000' Device 'gpio@5d0b0000': seq 2 is in use by 'gpio@5d0a0000' => dm uclass uclass 36: gpio 0 * gpio@5d080000 @ fbaefb90, seq 0, (req -1) 1 * gpio@5d090000 @ fbaefc70, seq 1, (req 0) 2 * gpio@5d0a0000 @ fbaefd50, seq 2, (req 1) 3 * gpio@5d0b0000 @ fbaefe30, seq 5, (req 2) 4 * gpio@5d0c0000 @ fbaeff10, seq 3, (req 3) 5 * gpio@5d0d0000 @ fbaefff0, seq 4, (req 4) 6 * gpio@5d0e0000 @ fbaf00d0, seq 6, (req 5) 7 * gpio@5d0f0000 @ fbaf01b0, seq 7, (req 6) Signed-off-by: Ye Li

ARM: imx: soc: Select default TEXT_BASE for MX7

2020-06-22T15:44:20Z

Select default U-Boot and SPL text base for the MX7 SoC. The U-Boot text base is picked as the one used by various MX7 boards. The SPL text base however is different. The SPL text base is set to 0x912000 instead of the usual 0x911000, that is because the 0x911000 value cannot work. Using 0x911000 as a SPL text base will result in the DCD header being placed below the 0x911000 address, which is a reserved SRAM area which must not be used. This will actually trigger eMMC boot failure on MX7D at least. Hence the increment. Update all boards affected by this SPL problem to the new SPL_TEXT_BASE. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: NXP i.MX U-Boot Team Cc: Peng Fan Cc: Stefano Babic

ARM: imx: soc: Switch BOARD_EARLY_INIT_F to imply on MX7

2020-06-22T15:44:13Z

There are systems where board_early_init_f() is plain empty. Switch the config option from "select" to "imply", to permit user to unset the BOARD_EARLY_INIT_F if it were to be empty. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: NXP i.MX U-Boot Team Cc: Peng Fan Cc: Stefano Babic

ARM: imx: ddr: Fill in missing DDRC ZQCTLx on i.MX7

2020-06-22T15:44:06Z

The iMX7 defines further DDRC ZQCTLx registers, however those were thus far missing from the list of registers and not programmed. On systems with LPDDR2 or DDR3, those registers must be programmed with correct values, otherwise the DRAM may not work. However, existing systems which worked without programming these registers before are now setting those registers to 0, which is the default value, so no functional change there. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: NXP i.MX U-Boot Team Cc: Peng Fan Cc: Stefano Babic

ARM: dts: imx6qdl-sabresd: Fix AR8031 phy-mode

2020-06-22T15:41:25Z

As per kernel commit 0672d22a1924 ("ARM: dts: imx: Fix the AR803X phy-mode) the correct phy-mode should be "rgmii-id", so fix it accordingly to fix the Ethernet regression. This problem has been exposed by commit: commit 13114f38e2ccea9386726d8b9831dfc310589548 Author: Vladimir Oltean Date: Thu May 7 00:11:51 2020 +0200 phy: atheros: Explicitly disable RGMII delays To eliminate any doubts about the out-of-reset value of the PHY, that the driver previously relied on. If bisecting shows that this commit breaks your board you probably have a wrong PHY interface mode. You probably want the PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode. Signed-off-by: Vladimir Oltean Acked-by: Joe Hershberger Signed-off-by: Fabio Estevam