u-boot.git/arch/arm, branch v2020.10

ARM: dts: stm32: Add missing dm-spl props for SPI NOR on AV96

2020-10-02T12:18:00Z

The u-boot,dm-spl DT props are missing on AV96, hence the pinmux and flash0 nodes are not included in the reduced SPL DT. This prevents SPI NOR boot from working at all. Fix this by filling them in. Signed-off-by: Marek Vasut Cc: Patrick Delaunay Cc: Patrice Chotard Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay

arm: dts: lx2160a: Add IO range

2020-09-24T15:27:32Z

Add IO range property to fix below error on uboot PCI: Failed autoconfig bar 18 Signed-off-by: Wasim Khan [Rebased] Signed-off-by: Priyanka Jain

armv8: dts: fsl-lx2160a: add gpio0 gpio1 gpio3 DT nodes

2020-09-24T15:27:32Z

add gpio0 gpio1 gpio3 DT nodes to fsl-lx21600.dtsi Signed-off-by: hui.song Reviewed-by: Heiko Schocher Reviewed-by: Priyanka Jain

armv8: lx2160a: fix reset sequence

2020-09-24T15:27:32Z

Make sure that SW_RST_REQ and RST_REQ_MSK are cleared before triggering hardware reset request. Signed-off-by: Thirupathaiah Annapureddy Signed-off-by: Meenakshi Aggarwal Reviewed-by: Priyanka Jain

arm64: Layerscape: Survive LPI one-way reset workaround

2020-09-24T15:27:32Z

The workaround of LPI one-way reset issue is broken by the series: https://patchwork.ozlabs.org/project/uboot/list/?series=192398 This patch is to add DT node for GIC RD tables and create corresponding reserved-memory node in kernel DT to fix it. Signed-off-by: Hou Zhiqiang Reviewed-by: Priyanka Jain

fsl-layerscape: enable dwc3 snooping feature

2020-09-24T15:27:32Z

Configure DWC3’s cache type to ‘cacheable’ for better performance. Actually related register definition and values are SoC specific, which means this setting is only applicable to Layerscape SoC, not generic for all platforms which have integrated DWC3 IP. Signed-off-by: Ran Wang Reviewed-by: Priyanka Jain

apalis-imx8qm: rename all occurences to apalis-imx8

2020-09-17T12:41:33Z

The Toradex product is called apalis-imx8 consisting of SoM with i.MX8QM and i.MX8QP SoCs. Signed-off-by: Philippe Schenker Reviewed-by: Igor Opaniuk

colibri-imx8qxp: rename all occurences to colibri-imx8x

2020-09-17T12:41:26Z

The Toradex product is called colibri-imx8x consisting of SoM with i.MX8QXP and i.MX8DX SoCs. Signed-off-by: Philippe Schenker Reviewed-by: Igor Opaniuk

ARM: mx6: ddr: Add support for iMX6UL/ULL/SL/SDL

2020-09-17T12:40:55Z

This patch adds support for iMX6UL/ULL/SL/SDL MMDC into the DDR calibration code. The difference between MX6DQ and MX6UL/ULL/SL is that the later SoCs have 2 SDQS registers, just like MX6SX, while the MX6DQ/MX6SDL has 8. Fixes: 4f4c128c65 ("ARM: mx6: ddr: Add support for iMX6SX") Signed-off-by: Marek Vasut Cc: Eric Nelson Cc: Fabio Estevam Cc: Stefano Babic Reviewed-by: Fabio Estevam

imx8mp: Remove parts MIMX8ML7 and MIMX8ML5 support

2020-09-17T12:40:22Z

Latest datasheet revE has removed MIMX8ML7D/5D/7C/5C parts, so update u-boot to remove decoding and support for those parts. Signed-off-by: Ye Li Signed-off-by: Peng Fan