u-boot.git/arch/blackfin/cpu/initcode.h, branch v2014.01Unnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/u-boot.git/atom/arch/blackfin/cpu/initcode.h?h=v2014.012013-03-04T05:42:06Zblackfin: bf60x: Port blackfin core architecture code to boot on bf60x.2013-03-04T05:42:06ZSonic Zhangsonic.zhang@analog.com2012-08-16T03:56:14Zurn:sha1:a2979dcdbeb39a01dc888090d2c736c2ad3f548d
Set up clocks, DDR controller, Nor flash controller, reboot,
serial port. Add new SPI boot modes.
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
Blackfin: split out async setup2011-07-12T06:17:46ZMike Frysingervapier@gentoo.org2011-05-30T17:47:38Zurn:sha1:4150cec3353b7a6d7a3ea71b2d3c62deafff353d
We really only need to tweak the async banks in the initcode if the
processor is booting out of it, otherwise we can wait until later
on in the CPU booting setup.
This also makes testing in the sim and early bring up over JTAG work
much smoother when the initcode gets bypassed.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>