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<title>u-boot.git/arch/microblaze/include/asm, branch v2024.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/microblaze/include/asm?h=v2024.07</id>
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<updated>2024-05-19T14:16:36Z</updated>
<entry>
<title>Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""</title>
<updated>2024-05-19T14:16:36Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-05-19T02:20:43Z</published>
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<id>urn:sha1:d678a59d2d719da9e807495b4b021501f2836ca5</id>
<content type='text'>
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.

This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.

Reported-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>global: Make &lt;asm/global_data.h&gt; include &lt;asm/u-boot.h&gt;</title>
<updated>2024-05-06T21:07:48Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-05-01T02:40:48Z</published>
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<id>urn:sha1:6a7185887b83a5cc334c7ce5bd65970381b2f4ce</id>
<content type='text'>
This follows the example of RISC-V where &lt;asm/global_data.h&gt; includes
&lt;asm/u-boot.h&gt; directly as "gd" includes a reference to bd_info already
and so the first must include the second anyhow. We then remove
&lt;asm/u-boot.h&gt; from all of the places which include references to "gd"
an so have &lt;asm/global_data.h&gt; already.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>microblaze: Remove common.h usage</title>
<updated>2023-10-24T20:34:45Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-10-12T23:03:57Z</published>
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<id>urn:sha1:577dddb5b7d6e0f962ea06ed80b85bc6ec5ca7d8</id>
<content type='text'>
We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
Acked-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
</entry>
<entry>
<title>treewide: rework linker symbol declarations in sections header</title>
<updated>2023-08-09T13:21:42Z</updated>
<author>
<name>Shiji Yang</name>
<email>yangshiji66@outlook.com</email>
</author>
<published>2023-08-03T01:47:16Z</published>
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<id>urn:sha1:506df9dc5881b74ca6463b89e9edcd14732a7da5</id>
<content type='text'>
1. Convert all linker symbols to char[] type so that we can get the
   corresponding address by calling array name 'var' or its address
   '&amp;var'. In this way, we can avoid some potential issues[1].
2. Remove unused symbol '_TEXT_BASE'. It has been abandoned and has
   not been referenced by any source code.
3. Move '__data_end' to the arch x86's own sections header as it's
   only used by x86 arch.
4. Remove some duplicate declared linker symbols. Now we use the
   standard header file to declare them.

[1] This patch fixes the boot failure on MIPS target. Error log:
SPL: Image overlaps SPL

Fixes: 1b8a1be1a1f1 ("spl: spl_legacy: Fix spl_end address")
Signed-off-by: Shiji Yang &lt;yangshiji66@outlook.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>arm64: zynqmp: Switch to amd.com emails</title>
<updated>2023-07-21T07:00:38Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@amd.com</email>
</author>
<published>2023-07-10T12:35:49Z</published>
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<id>urn:sha1:174d728471d50415fb60f4bcb560d0552591dfba</id>
<content type='text'>
Update my and DPs email address to match current setup.

Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
</content>
</entry>
<entry>
<title>Correct SPL uses of CPU_MICROBLAZE</title>
<updated>2023-02-09T21:32:26Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2023-02-05T22:39:31Z</published>
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<id>urn:sha1:7c31107249da086c44cd4ab930941c921a233a6e</id>
<content type='text'>
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_CPU_MICROBLAZE defined in Kconfig

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>Convert CONFIG_SYS_BOOT_RAMDISK_HIGH to Kconfig</title>
<updated>2022-07-07T18:01:09Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2022-06-25T15:02:46Z</published>
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<id>urn:sha1:bb20a105e9fa475eb4258086cf59173540e7ff23</id>
<content type='text'>
This converts the following to Kconfig:
   CONFIG_SYS_BOOT_RAMDISK_HIGH

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>microblaze: Remove interrupt handler</title>
<updated>2022-06-24T12:16:32Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@amd.com</email>
</author>
<published>2022-06-24T12:16:32Z</published>
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<id>urn:sha1:aec051d813906f2a52b840d0d12a0764370aba1a</id>
<content type='text'>
The primary purpose for this code was timer. By converting it to
CONFIG_TIMER there is no code which uses this implementation that's why
remove it. If there is a need to handle interrupts this patch can be
reverted in future.

Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/5f2decc5a30a5678490ebde26d8c6f5a5f873cda.1654684731.git.michal.simek@amd.com
</content>
</entry>
<entry>
<title>microblaze: Convert axi timer to DM driver</title>
<updated>2022-06-24T12:16:32Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@amd.com</email>
</author>
<published>2022-06-24T12:16:32Z</published>
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<id>urn:sha1:a36d86720f23a6dd503073a82905002b88c8e363</id>
<content type='text'>
Move axi timer driver from Microblaze to generic location.
Origin implementation was irq based with counting down timer.

CONFIG_TIMER drivers are designed differently that timer is free running up
timer with automatic reload without any interrupt.
Information about clock rates are find out in timer_pre_probe() that's why
there is no need to get any additional information from DT in the driver
itself (only register offset).

Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Tested-by: Ovidiu Panait &lt;ovidiu.panait@windriver.com&gt;
Link: https://lore.kernel.org/r/6c12fc86bbc1f17d05c25018862e7b7b03346b36.1654684731.git.michal.simek@amd.com
</content>
</entry>
<entry>
<title>cpu: add CPU driver for microblaze</title>
<updated>2022-06-24T12:16:00Z</updated>
<author>
<name>Ovidiu Panait</name>
<email>ovpanait@gmail.com</email>
</author>
<published>2022-05-31T18:14:35Z</published>
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<id>urn:sha1:816226d27efa22d89821dfd0796f763a24c33944</id>
<content type='text'>
Add a basic CPU driver that retrieves information about the microblaze CPU
core. cpu_ops handlers are implemented so that the "cpu" command can work
properly:

U-Boot-mONStR&gt; cpu list
  0: cpu@0      MicroBlaze @ 50MHz, Rev: 11.0, FPGA family: zynq7000
U-Boot-mONStR&gt; cpu detail
  0: cpu@0      MicroBlaze @ 50MHz, Rev: 11.0, FPGA family: zynq7000
        ID = 0, freq = 50 MHz: L1 cache, MMU

Note: cpu_ver_lookup[] and family_string_lookup[] arrays were imported from
linux.

Signed-off-by: Ovidiu Panait &lt;ovpanait@gmail.com&gt;
Link: https://lore.kernel.org/r/20220531181435.3473549-14-ovpanait@gmail.com
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
</entry>
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