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<title>u-boot.git/arch/microblaze/lib, branch v2024.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/microblaze/lib?h=v2024.01</id>
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<updated>2023-10-24T20:34:45Z</updated>
<entry>
<title>microblaze: Remove common.h usage</title>
<updated>2023-10-24T20:34:45Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-10-12T23:03:57Z</published>
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<id>urn:sha1:577dddb5b7d6e0f962ea06ed80b85bc6ec5ca7d8</id>
<content type='text'>
We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
Acked-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
</entry>
<entry>
<title>Correct SPL uses of LMB</title>
<updated>2023-02-10T12:41:39Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2023-02-05T22:40:13Z</published>
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<id>urn:sha1:210af54947e1b88f1fb961fec51d6427f5ec8575</id>
<content type='text'>
This converts 9 usages of this option to the non-SPL form, since there is
no SPL_LMB defined in Kconfig

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>treewide: Drop bootm_headers_t typedef</title>
<updated>2022-09-29T20:07:57Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2022-09-07T02:26:50Z</published>
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<id>urn:sha1:d9d7c20b731788c5c8018ce8e5c6e86bb01413df</id>
<content type='text'>
This is not needed and we should avoid typedefs. Use the struct instead.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>microblaze: add arch_print_bdinfo() implementation</title>
<updated>2022-09-13T09:32:48Z</updated>
<author>
<name>Ovidiu Panait</name>
<email>ovpanait@gmail.com</email>
</author>
<published>2022-08-29T17:02:05Z</published>
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<id>urn:sha1:f459986e86458a9980a3d0f4de1d4a44a549c00c</id>
<content type='text'>
Allow bdinfo command to print icache/dcache information:
U-Boot-mONStR&gt; bdinfo
boot_params = 0x00000000
DRAM bank   = 0x00000000
-&gt; start    = 0x04000000
-&gt; size     = 0x04000000
flashstart  = 0x00000000
flashsize   = 0x00000000
flashoffset = 0x00000000
baudrate    = 9600 bps
relocaddr   = 0x07f76000
reloc off   = 0x02f76000
Build       = 32-bit
current eth = unknown
ethaddr     = (not set)
IP addr     = &lt;NULL&gt;
fdt_blob    = 0x07fec7e0
new_fdt     = 0x00000000
fdt_size    = 0x00000000
lmb_dump_all:
 memory.cnt  = 0x1
 memory[0]      [0x4000000-0x7ffffff], 0x04000000 bytes flags: 0
 reserved.cnt  = 0x1
 reserved[0]    [0x7e94b8c-0x7ffffff], 0x0016b474 bytes flags: 0
devicetree  = embed
icache      = 32 KiB
icache line = 4 Bytes
dcache      = 32 KiB
dcache line = 4 Bytes

Signed-off-by: Ovidiu Panait &lt;ovpanait@gmail.com&gt;
Link: https://lore.kernel.org/r/20220829170205.1274484-4-ovpanait@gmail.com
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
</entry>
<entry>
<title>zynqmp: Run board_get_usable_ram_top() only on main U-Boot</title>
<updated>2022-07-26T06:23:54Z</updated>
<author>
<name>Ashok Reddy Soma</name>
<email>ashok.reddy.soma@xilinx.com</email>
</author>
<published>2022-07-07T08:45:37Z</published>
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<id>urn:sha1:65168910adaae3a4ac91fd5acf30941a28facc0e</id>
<content type='text'>
With commit ce39ee28ec31 ("zynqmp: Do not place u-boot to reserved memory
location"), the function board_get_usable_ram_top() is allocating
MMU_SECTION_SIZE of about 2MB using lmb_alloc(). But we dont have this
much memory in case of mini U-Boot.

Keep these functions which use lmb under CONFIG_LMB so that they are
compiled and used only when LMB is enabled.

Signed-off-by: Ashok Reddy Soma &lt;ashok.reddy.soma@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;

Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/75e52def75f573e554a6b177a78504c128cb0c4a.1657183534.git.michal.simek@amd.com
</content>
</entry>
<entry>
<title>microblaze: cache: introduce flush_cache_all()</title>
<updated>2022-06-24T12:16:00Z</updated>
<author>
<name>Ovidiu Panait</name>
<email>ovpanait@gmail.com</email>
</author>
<published>2022-05-31T18:14:30Z</published>
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<id>urn:sha1:b195134984ec714f92632704e4725ced170ab1da</id>
<content type='text'>
All flush_cache() calls in microblaze code are supposed to flush the
entire instruction and data caches, so introduce flush_cache_all()
helper to handle this.

Also, provide implementations for flush_dcache_all() and
invalidate_icache_all() so that icache and dcache u-boot commands can
work.

Signed-off-by: Ovidiu Panait &lt;ovpanait@gmail.com&gt;
Link: https://lore.kernel.org/r/20220531181435.3473549-9-ovpanait@gmail.com
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
</entry>
<entry>
<title>microblaze: cache: introduce Kconfig options for icache/dcache sizes</title>
<updated>2022-06-24T12:16:00Z</updated>
<author>
<name>Ovidiu Panait</name>
<email>ovpanait@gmail.com</email>
</author>
<published>2022-05-31T18:14:29Z</published>
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<id>urn:sha1:84488fc69348367ee693ea4ab6affe3cbcae97a0</id>
<content type='text'>
Replace XILINX_DCACHE_BYTE_SIZE macro with two Kconfig symbols for
instruction and data caches sizes, respectively:
CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE
CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE

Also, get rid of the hardcoded value in icache_disable().

Signed-off-by: Ovidiu Panait &lt;ovpanait@gmail.com&gt;
Link: https://lore.kernel.org/r/20220531181435.3473549-8-ovpanait@gmail.com
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt; (s/bralid/brlid/g)
</content>
</entry>
<entry>
<title>microblaze: cache: improve dcache Kconfig options</title>
<updated>2022-06-24T12:16:00Z</updated>
<author>
<name>Ovidiu Panait</name>
<email>ovpanait@gmail.com</email>
</author>
<published>2022-05-31T18:14:26Z</published>
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<id>urn:sha1:ef0a592ae8e2961519510f48ffe48b655b31610a</id>
<content type='text'>
Replace CONFIG_DCACHE with a Kconfig option more limited in scope -
XILINX_MICROBLAZE0_USE_WDC. It should be enabled if the processor supports
the "wdc" (Write to Data Cache) instruction. It will be used to guard
"wdc" invocations in microblaze cache code.

Also, drop all ifdefs around flush_cache() calls and only keep one
CONFIG_IS_ENABLED() guard within flush_cache() itself.

Signed-off-by: Ovidiu Panait &lt;ovpanait@gmail.com&gt;
Link: https://lore.kernel.org/r/20220531181435.3473549-5-ovpanait@gmail.com
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
</entry>
<entry>
<title>microblaze: cache: replace XILINX_USE_DCACHE -&gt; CONFIG_DCACHE</title>
<updated>2022-06-24T12:16:00Z</updated>
<author>
<name>Ovidiu Panait</name>
<email>ovpanait@gmail.com</email>
</author>
<published>2022-05-31T18:14:25Z</published>
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<id>urn:sha1:0ad71dc53af000609d4484a465e630e569e73d63</id>
<content type='text'>
XILINX_USE_DCACHE macro was removed in 7556fa09e0e ("microblaze: Simplify
cache handling"), but it was still used in a couple of places.

Replace those occurences with CONFIG_DCACHE.

Signed-off-by: Ovidiu Panait &lt;ovpanait@gmail.com&gt;
Link: https://lore.kernel.org/r/20220531181435.3473549-4-ovpanait@gmail.com
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
</entry>
<entry>
<title>image: Drop IMAGE_ENABLE_OF_LIBFDT</title>
<updated>2021-10-08T19:53:26Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2021-09-26T01:43:21Z</published>
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<id>urn:sha1:0c303f9a6628de9664b4f9140464a6f9d8224c36</id>
<content type='text'>
Add a host Kconfig for OF_LIBFDT. With this we can use
CONFIG_IS_ENABLED(OF_LIBFDT) directly in the tools build, so drop the
unnecessary indirection.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Alexandru Gagniuc &lt;mr.nuke.me@gmail.com&gt;
</content>
</entry>
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