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<title>u-boot.git/arch/microblaze, branch v2023.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/microblaze?h=v2023.01</id>
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<updated>2022-10-31T15:01:31Z</updated>
<entry>
<title>Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASE</title>
<updated>2022-10-31T15:01:31Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2022-10-21T00:22:39Z</published>
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<id>urn:sha1:984639039f4cfe32ec2cc531d6ace05326ac49eb</id>
<content type='text'>
The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE
and this makes it imposible to use CONFIG_VAL().

Rename it to resolve this problem.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>treewide: Drop bootm_headers_t typedef</title>
<updated>2022-09-29T20:07:57Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2022-09-07T02:26:50Z</published>
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<id>urn:sha1:d9d7c20b731788c5c8018ce8e5c6e86bb01413df</id>
<content type='text'>
This is not needed and we should avoid typedefs. Use the struct instead.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>microblaze: add arch_print_bdinfo() implementation</title>
<updated>2022-09-13T09:32:48Z</updated>
<author>
<name>Ovidiu Panait</name>
<email>ovpanait@gmail.com</email>
</author>
<published>2022-08-29T17:02:05Z</published>
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<id>urn:sha1:f459986e86458a9980a3d0f4de1d4a44a549c00c</id>
<content type='text'>
Allow bdinfo command to print icache/dcache information:
U-Boot-mONStR&gt; bdinfo
boot_params = 0x00000000
DRAM bank   = 0x00000000
-&gt; start    = 0x04000000
-&gt; size     = 0x04000000
flashstart  = 0x00000000
flashsize   = 0x00000000
flashoffset = 0x00000000
baudrate    = 9600 bps
relocaddr   = 0x07f76000
reloc off   = 0x02f76000
Build       = 32-bit
current eth = unknown
ethaddr     = (not set)
IP addr     = &lt;NULL&gt;
fdt_blob    = 0x07fec7e0
new_fdt     = 0x00000000
fdt_size    = 0x00000000
lmb_dump_all:
 memory.cnt  = 0x1
 memory[0]      [0x4000000-0x7ffffff], 0x04000000 bytes flags: 0
 reserved.cnt  = 0x1
 reserved[0]    [0x7e94b8c-0x7ffffff], 0x0016b474 bytes flags: 0
devicetree  = embed
icache      = 32 KiB
icache line = 4 Bytes
dcache      = 32 KiB
dcache line = 4 Bytes

Signed-off-by: Ovidiu Panait &lt;ovpanait@gmail.com&gt;
Link: https://lore.kernel.org/r/20220829170205.1274484-4-ovpanait@gmail.com
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
</entry>
<entry>
<title>zynqmp: Run board_get_usable_ram_top() only on main U-Boot</title>
<updated>2022-07-26T06:23:54Z</updated>
<author>
<name>Ashok Reddy Soma</name>
<email>ashok.reddy.soma@xilinx.com</email>
</author>
<published>2022-07-07T08:45:37Z</published>
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<id>urn:sha1:65168910adaae3a4ac91fd5acf30941a28facc0e</id>
<content type='text'>
With commit ce39ee28ec31 ("zynqmp: Do not place u-boot to reserved memory
location"), the function board_get_usable_ram_top() is allocating
MMU_SECTION_SIZE of about 2MB using lmb_alloc(). But we dont have this
much memory in case of mini U-Boot.

Keep these functions which use lmb under CONFIG_LMB so that they are
compiled and used only when LMB is enabled.

Signed-off-by: Ashok Reddy Soma &lt;ashok.reddy.soma@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;

Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/75e52def75f573e554a6b177a78504c128cb0c4a.1657183534.git.michal.simek@amd.com
</content>
</entry>
<entry>
<title>Convert CONFIG_SYS_BOOT_RAMDISK_HIGH to Kconfig</title>
<updated>2022-07-07T18:01:09Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2022-06-25T15:02:46Z</published>
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<id>urn:sha1:bb20a105e9fa475eb4258086cf59173540e7ff23</id>
<content type='text'>
This converts the following to Kconfig:
   CONFIG_SYS_BOOT_RAMDISK_HIGH

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'xilinx-for-v2022.10' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next</title>
<updated>2022-06-27T14:15:50Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2022-06-27T14:15:50Z</published>
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<id>urn:sha1:c316ee674f25b73285f241ce922307296616a92a</id>
<content type='text'>
Xilinx changes for v2022.10

cpu:
- Add driver for microblaze cpu

net:
- Add support for DM_ETH_PHY to AXI emac and emaclite

xilinx:
- Switch platforms to DM_ETH_PHY
- DT chagnes in ZynqMP and Zynq
- Enable support for SquashFS

zynqmp:
- Add support for KR260 boards
- Move BSS from address 0
- Move platform identification from board code to soc driver
- Improve zynqmp_psu_init_minimize

versal:
- Enable loading app at EL1

serial:
- Setup default address and clock rates for DEBUG uarts

pinctrl:
- Add support for tri state and output enable properties

relocate-rela:
- Clean relocate-rela implementation for ARM64
- Add support for Microblaze

microblaze:
- Add support for runtime relocation
- Rework cache handling (wiring, Kconfig) based on cpuinfo
- Remove interrupt support

timer:
- Extract axi timer driver from Microblaze to generic location
</content>
</entry>
<entry>
<title>microblaze: Remove interrupt handler</title>
<updated>2022-06-24T12:16:32Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@amd.com</email>
</author>
<published>2022-06-24T12:16:32Z</published>
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<id>urn:sha1:aec051d813906f2a52b840d0d12a0764370aba1a</id>
<content type='text'>
The primary purpose for this code was timer. By converting it to
CONFIG_TIMER there is no code which uses this implementation that's why
remove it. If there is a need to handle interrupts this patch can be
reverted in future.

Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/5f2decc5a30a5678490ebde26d8c6f5a5f873cda.1654684731.git.michal.simek@amd.com
</content>
</entry>
<entry>
<title>microblaze: Convert axi timer to DM driver</title>
<updated>2022-06-24T12:16:32Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@amd.com</email>
</author>
<published>2022-06-24T12:16:32Z</published>
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<id>urn:sha1:a36d86720f23a6dd503073a82905002b88c8e363</id>
<content type='text'>
Move axi timer driver from Microblaze to generic location.
Origin implementation was irq based with counting down timer.

CONFIG_TIMER drivers are designed differently that timer is free running up
timer with automatic reload without any interrupt.
Information about clock rates are find out in timer_pre_probe() that's why
there is no need to get any additional information from DT in the driver
itself (only register offset).

Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Tested-by: Ovidiu Panait &lt;ovidiu.panait@windriver.com&gt;
Link: https://lore.kernel.org/r/6c12fc86bbc1f17d05c25018862e7b7b03346b36.1654684731.git.michal.simek@amd.com
</content>
</entry>
<entry>
<title>cpu: add CPU driver for microblaze</title>
<updated>2022-06-24T12:16:00Z</updated>
<author>
<name>Ovidiu Panait</name>
<email>ovpanait@gmail.com</email>
</author>
<published>2022-05-31T18:14:35Z</published>
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<id>urn:sha1:816226d27efa22d89821dfd0796f763a24c33944</id>
<content type='text'>
Add a basic CPU driver that retrieves information about the microblaze CPU
core. cpu_ops handlers are implemented so that the "cpu" command can work
properly:

U-Boot-mONStR&gt; cpu list
  0: cpu@0      MicroBlaze @ 50MHz, Rev: 11.0, FPGA family: zynq7000
U-Boot-mONStR&gt; cpu detail
  0: cpu@0      MicroBlaze @ 50MHz, Rev: 11.0, FPGA family: zynq7000
        ID = 0, freq = 50 MHz: L1 cache, MMU

Note: cpu_ver_lookup[] and family_string_lookup[] arrays were imported from
linux.

Signed-off-by: Ovidiu Panait &lt;ovpanait@gmail.com&gt;
Link: https://lore.kernel.org/r/20220531181435.3473549-14-ovpanait@gmail.com
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
</entry>
<entry>
<title>microblaze: add support for handling PVR data</title>
<updated>2022-06-24T12:16:00Z</updated>
<author>
<name>Ovidiu Panait</name>
<email>ovpanait@gmail.com</email>
</author>
<published>2022-05-31T18:14:34Z</published>
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<id>urn:sha1:9df16c5937f68654fb2b67f932319c375f8e4e45</id>
<content type='text'>
Add helper code for PVR (Processor Version Register) data handling. It
will be used by the UCLASS_CPU driver to populate cpuinfo fields at
runtime.

Signed-off-by: Ovidiu Panait &lt;ovpanait@gmail.com&gt;
Link: https://lore.kernel.org/r/20220531181435.3473549-13-ovpanait@gmail.com
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
</entry>
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