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<title>u-boot.git/arch/mips/Kconfig, branch v2016.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/mips/Kconfig?h=v2016.09</id>
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<updated>2016-06-10T10:27:37Z</updated>
<entry>
<title>MIPS: Make CONFIG_SYS_DCACHE_LINE_SIZE int, not hex</title>
<updated>2016-06-10T10:27:37Z</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2016-06-09T12:09:52Z</published>
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<id>urn:sha1:4b7b0a0f0635c1d1e4a0ae2ed172530b5f78e74b</id>
<content type='text'>
For consistency with the other cache-related Kconfig entries &amp; the
values actually set by boards, make CONFIG_SYS_DCACHE_LINE_SIZE an int
entry instead of a hex entry.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
Fixes: 372286217f05 ("MIPS: Split I &amp; D cache line size config")
</content>
</entry>
<entry>
<title>MIPS: Split I &amp; D cache line size config</title>
<updated>2016-05-31T07:44:24Z</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2016-05-27T13:28:05Z</published>
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<id>urn:sha1:372286217f050bfd57695001d59f618c52822f40</id>
<content type='text'>
Allow L1 Icache &amp; L1 Dcache line size to be specified separately, since
there's no architectural mandate that they be the same. The
[id]cache_line_size functions are tidied up to take advantage of the
fact that the Kconfig entries are always present to simply check them
for zero rather than needing to #ifdef on their presence.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
[removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h]
Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
</entry>
<entry>
<title>MIPS: Move cache sizes to Kconfig</title>
<updated>2016-05-31T07:44:24Z</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2016-05-27T13:28:04Z</published>
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<id>urn:sha1:ace3be4f15875d74344336b9754c14274f940969</id>
<content type='text'>
Move details of the L1 cache line sizes &amp; total sizes into Kconfig,
defaulting to 0. A new CONFIG_SYS_CACHE_SIZE_AUTO Kconfig entry is
introduced to allow platforms to select auto-detection of cache sizes,
and it defaults to being enabled if none of the cache sizes are set by
the configuration (ie. sizes are all the default 0), and code is
adjusted to #ifdef on that rather than on the definition of the sizes
(which will always be defined even if 0).

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
</content>
</entry>
<entry>
<title>MIPS: add tune for MIPS 34kc</title>
<updated>2016-05-31T07:38:11Z</updated>
<author>
<name>Daniel Schwierzeck</name>
<email>daniel.schwierzeck@gmail.com</email>
</author>
<published>2016-05-27T13:39:39Z</published>
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<id>urn:sha1:5f9cc363ed9b68245cacc6408c793f150992f4d9</id>
<content type='text'>
Add tune Kconfig option for MIPS 34kc.

Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
</entry>
<entry>
<title>malta: Allow MIPS64 builds</title>
<updated>2016-05-31T07:38:11Z</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2016-05-26T13:49:36Z</published>
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<id>urn:sha1:0f832b9cdcbe8a024b53c585622d70129652d20b</id>
<content type='text'>
Both real Malta boards &amp; emulators that mimic Malta (eg. QEMU) can
support MIPS64 CPUs. Allow MIPS64 builds of U-Boot for such boards,
which enables the user to make use of the whole 64 bit address space.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
</content>
</entry>
<entry>
<title>malta: Use device model &amp; tree for UART</title>
<updated>2016-05-25T23:34:13Z</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2016-05-17T06:43:28Z</published>
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<id>urn:sha1:6242aa137427f6da6ca47e7a8c9a9f78ad63e00d</id>
<content type='text'>
Make use of device model &amp; device tree to probe the UART driver. This is
the initial step in bringing Malta up to date with driver model, and
allows for cleaner handling of the different I/O addresses for different
system controllers by specifying the ISA bus address instead of a
translated memory address.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
</entry>
<entry>
<title>malta: Support MIPS32r6 configurations</title>
<updated>2016-05-20T23:36:39Z</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2016-05-16T09:52:14Z</published>
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<id>urn:sha1:40ba13c98627055465709acd67872e381b42f928</id>
<content type='text'>
Both real Malta boards &amp; QEMU's Malta emulation can feature MIPS32r6
CPUs. Allow building U-Boot for such systems by selecting
CONFIG_SUPPORTS_CPU_MIPS32_R6 for Malta.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
</content>
</entry>
<entry>
<title>MIPS: Support for targetting MIPSr6</title>
<updated>2016-05-20T23:36:39Z</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2016-05-16T09:52:12Z</published>
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<id>urn:sha1:c52ebea1ccb6f8cdd0b1d883056d215c715a5920</id>
<content type='text'>
Add support for targetting MIPS32r6 &amp; MIPS64r6 systems, in the same way
that we currently select release 1 or release 2 targets. MIPSr6 is not
entirely backwards compatible with earlier releases of the architecture.
Some instructions are encoded differently, some are removed, some are
reused, so it is not practical to run U-Boot built for earlier revisions
on a MIPSr6 system. Update their Kconfig help text to reflect that.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
</content>
</entry>
<entry>
<title>MIPS: Simplify CONFIG_SYS_CPU values</title>
<updated>2016-05-20T23:36:39Z</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2016-05-16T09:52:11Z</published>
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<id>urn:sha1:20286cdff766d64dc718a9d855b049580dfeb3cc</id>
<content type='text'>
Rather than having the values for CONFIG_SYS_CPU depend upon each
architecture revision, have them depend upon the more general
CONFIG_CPU_MIPS32 &amp; CONFIG_CPU_MIPS64 which in turn depend upon the
architecture revisions.

This is done in preparation for adding MIPSr6 support, which would
otherwise need to introduce new cases here.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
</content>
</entry>
<entry>
<title>mips: Add MIPS 74Kc tune</title>
<updated>2016-05-20T23:36:38Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2016-05-06T18:10:33Z</published>
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<id>urn:sha1:0a0a958b68ee9d78a7cbccb5f72b95e1d488c9bd</id>
<content type='text'>
Add MIPS 74Kc tune Kconfig option.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Cc: Wills Wang &lt;wills.wang@live.com&gt;
[added missing tune-y entry in arch/mips/Makefile]
Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
</entry>
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