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<title>u-boot.git/arch/mips/Kconfig, branch v2017.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/mips/Kconfig?h=v2017.09</id>
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<updated>2017-08-16T00:50:01Z</updated>
<entry>
<title>env: Convert CONFIG_ENV_IS_IN... to a choice</title>
<updated>2017-08-16T00:50:01Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2017-08-03T18:21:59Z</published>
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<id>urn:sha1:c1c3fe23070ac924e65208abbf8d2396bcc08008</id>
<content type='text'>
At present we support multiple environment drivers but there is not way to
select between them at run time. Also settings related to the position and
size of the environment area are global (i.e. apply to all locations).

Until these limitations are removed we cannot really support more than one
environment location. Adjust the location to be a choice so that only one
can be selected. By default the environment is 'nowhere', meaning that the
environment exists only in memory and cannot be saved.

Also expand the help for the 'nowhere' option and move it to the top since
it is the default.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
[trini: Move all of the imply logic to default X if Y so it works again]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>Convert CONFIG_ENV_IS_IN_FLASH to Kconfig</title>
<updated>2017-07-26T01:20:02Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2017-07-24T03:19:41Z</published>
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<id>urn:sha1:85fc970d74d09f33fcdcc649e73c5dc4f5334605</id>
<content type='text'>
This converts the following to Kconfig:
   CONFIG_ENV_IS_IN_FLASH

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>Convert CONFIG_ENV_IS_IN_MMC/NAND/UBI and NOWHERE to Kconfig</title>
<updated>2017-07-26T01:08:01Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2017-07-24T03:19:39Z</published>
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<id>urn:sha1:2be296538e2e9d2893dc495b3fc8f9f6acb1454c</id>
<content type='text'>
This converts the following to Kconfig:
   CONFIG_ENV_IS_IN_MMC
   CONFIG_ENV_IS_IN_NAND
   CONFIG_ENV_IS_IN_UBI
   CONFIG_ENV_IS_NOWHERE

In fact this already exists for sunxi as a 'choice' config. However not
all the choices are available in Kconfig yet so we cannot use that. It
would lead to more than one option being set.

In addition, one purpose of this series is to allow the environment to be
stored in more than one place. So the existing choice is converted to a
normal config allowing each option to be set independently.

There are not many opportunities for Kconfig updates to reduce the size of
this patch. This was tested with

   ./tools/moveconfig.py -i CONFIG_ENV_IS_IN_MMC

And then manual updates.  This is because for CHAIN_OF_TRUST boards they
can only have ENV_IS_NOWHERE set, so we enforce that via Kconfig logic
now.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>boston: Setup memory ranges in FDT provided to Linux</title>
<updated>2017-05-12T11:29:50Z</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2017-04-30T19:22:42Z</published>
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<id>urn:sha1:d2b12a5767ec762f92a7c308a562472e23b5347e</id>
<content type='text'>
The boston memory map isn't suited to the simple "all memory starting
from 0" approach that the MIPS arch_fixup_fdt() implementation takes.
Instead we need to indicate the first 256MiB of DDR from 0 and the rest
from 0x90000000. Implement ft_board_setup to do that.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>boston: Move CM GCRs away from flash</title>
<updated>2017-05-12T11:29:50Z</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2017-04-30T19:22:41Z</published>
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<id>urn:sha1:ed048e7c763ac9b7043c989ba3081d7a52e4f68e</id>
<content type='text'>
Move the MIPS Coherence Manager (CM) Global Configuration Registers
(GCRs) away from the region of the physical address space which the
Boston board's parallel flash is found in, such that we can access all
of flash without clobbering GCRs.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Make CM GCR base configurable</title>
<updated>2017-05-12T11:29:50Z</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2017-05-12T11:26:11Z</published>
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<id>urn:sha1:939a255a671fb50549848505a4b44369cbe08efd</id>
<content type='text'>
Without adding a prompt for CONFIG_MIPS_CM_BASE, Kconfig doesn't allow
defconfigs to set it. Provide the prompt in order to allow for that.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>MIPS: add initial infrastructure for Broadcom MIPS SoCs</title>
<updated>2017-05-10T14:16:09Z</updated>
<author>
<name>Álvaro Fernández Rojas</name>
<email>noltari@gmail.com</email>
</author>
<published>2017-04-24T22:39:20Z</published>
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<id>urn:sha1:ee422142f454d54f0ed39a2cbf083ff12e98a3e1</id>
<content type='text'>
CFE checks CPU Thread in a different way (using register $22):
mfc0	t1, C0_BCM_CONFIG, 3 # $22
li	t2, CP0_CMT_TPID # (1 &lt;&lt; 31)
and	t1, t2
bnez	t1, 2f	# if we are running on thread 1, skip init
nop

Signed-off-by: Álvaro Fernández Rojas &lt;noltari@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>MIPS: add possibility to setup initial stack and global data in SRAM</title>
<updated>2016-11-30T15:11:46Z</updated>
<author>
<name>Daniel Schwierzeck</name>
<email>daniel.schwierzeck@gmail.com</email>
</author>
<published>2016-06-04T14:13:21Z</published>
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<id>urn:sha1:924ad86638705fe37db98812f355260669f0f043</id>
<content type='text'>
This adds a new Kconfig option CONFIG_MIPS_INIT_STACK_IN_SRAM which
a SoC can select if it supports some kind of SRAM. Together with
CONFIG_SYS_INIT_SP_ADDR the initial stack and global data can be
set up in that SRAM. This can be used to provide a C environment
also for lowlevel_init().

Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
</entry>
<entry>
<title>MIPS: make inclusion of ROM exception vectors configurable</title>
<updated>2016-11-30T15:07:17Z</updated>
<author>
<name>Daniel Schwierzeck</name>
<email>daniel.schwierzeck@gmail.com</email>
</author>
<published>2016-02-14T17:52:57Z</published>
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<id>urn:sha1:af3971f81ac0fc344461cf86af682ecf1ebe18a8</id>
<content type='text'>
This adds a compile time option to include code for static
exception vectors. Static exception vectors are only needed,
when the U-Boot entry point is equal to the CPU reset exception
vector address. For instance this is the case when U-Boot is
used as ROM in Qemu or booted from parallel NOR flash. When
U-Boot is booted from RAM (e.g. loaded there by SPL), the
exception vectors need to be setup dynamically, which is done
in follow-up commits.

Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
</entry>
<entry>
<title>boston: Introduce support for the MIPS Boston development board</title>
<updated>2016-09-21T14:24:36Z</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2016-09-08T06:47:39Z</published>
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<id>urn:sha1:ad8783cb1cb258b71d81800f72cd64eb44081653</id>
<content type='text'>
This patch introduces support for building U-Boot to run on the MIPS
Boston development board. This is a board built around an FPGA &amp; an
Intel EG20T Platform Controller Hub, used largely as part of the
development of new CPUs and their software support. It is essentially
the successor to the older MIPS Malta board.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
</content>
</entry>
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