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<title>u-boot.git/arch/mips/Makefile, branch v2018.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/mips/Makefile?h=v2018.07</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/arch/mips/Makefile?h=v2018.07'/>
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<updated>2018-05-07T13:34:12Z</updated>
<entry>
<title>SPDX: Convert all of our single license tags to Linux Kernel style</title>
<updated>2018-05-07T13:34:12Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-05-06T21:58:06Z</published>
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<id>urn:sha1:83d290c56fab2d38cd1ab4c4cc7099559c1d5046</id>
<content type='text'>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>MIPS: add initial infrastructure for Broadcom MIPS SoCs</title>
<updated>2017-05-10T14:16:09Z</updated>
<author>
<name>Álvaro Fernández Rojas</name>
<email>noltari@gmail.com</email>
</author>
<published>2017-04-24T22:39:20Z</published>
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<id>urn:sha1:ee422142f454d54f0ed39a2cbf083ff12e98a3e1</id>
<content type='text'>
CFE checks CPU Thread in a different way (using register $22):
mfc0	t1, C0_BCM_CONFIG, 3 # $22
li	t2, CP0_CMT_TPID # (1 &lt;&lt; 31)
and	t1, t2
bnez	t1, 2f	# if we are running on thread 1, skip init
nop

Signed-off-by: Álvaro Fernández Rojas &lt;noltari@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>MIPS: add tune for MIPS 34kc</title>
<updated>2016-05-31T07:38:11Z</updated>
<author>
<name>Daniel Schwierzeck</name>
<email>daniel.schwierzeck@gmail.com</email>
</author>
<published>2016-05-27T13:39:39Z</published>
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<id>urn:sha1:5f9cc363ed9b68245cacc6408c793f150992f4d9</id>
<content type='text'>
Add tune Kconfig option for MIPS 34kc.

Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
</entry>
<entry>
<title>mips: Allow overriding start.S in SPL</title>
<updated>2016-05-25T23:34:14Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2016-05-25T00:17:42Z</published>
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<id>urn:sha1:ecc9d26062c9dd6d0752c988a54b95453c20c749</id>
<content type='text'>
Certain chips, like the JZ47xx, have extreme size constraints on the
SPL size and require custom start.S . Allow overriding the start.S
the same way ARM MXS does it.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Cc: Paul Burton &lt;paul.burton@imgtec.com&gt;
</content>
</entry>
<entry>
<title>MIPS: Support for targetting MIPSr6</title>
<updated>2016-05-20T23:36:39Z</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2016-05-16T09:52:12Z</published>
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<id>urn:sha1:c52ebea1ccb6f8cdd0b1d883056d215c715a5920</id>
<content type='text'>
Add support for targetting MIPS32r6 &amp; MIPS64r6 systems, in the same way
that we currently select release 1 or release 2 targets. MIPSr6 is not
entirely backwards compatible with earlier releases of the architecture.
Some instructions are encoded differently, some are removed, some are
reused, so it is not practical to run U-Boot built for earlier revisions
on a MIPSr6 system. Update their Kconfig help text to reflect that.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
</content>
</entry>
<entry>
<title>mips: Add MIPS 74Kc tune</title>
<updated>2016-05-20T23:36:38Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2016-05-06T18:10:33Z</published>
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<id>urn:sha1:0a0a958b68ee9d78a7cbccb5f72b95e1d488c9bd</id>
<content type='text'>
Add MIPS 74Kc tune Kconfig option.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Cc: Wills Wang &lt;wills.wang@live.com&gt;
[added missing tune-y entry in arch/mips/Makefile]
Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
</entry>
<entry>
<title>mips: add base support for QCA/Atheros ath79 SOCs</title>
<updated>2016-05-20T23:25:50Z</updated>
<author>
<name>Wills Wang</name>
<email>wills.wang@live.com</email>
</author>
<published>2016-03-16T08:59:52Z</published>
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<id>urn:sha1:1d3d0f1f1cd8bac8ea0135c92a2bcd5020abfb1d</id>
<content type='text'>
This patch add some common code for QCA/Atheros ath79 SOCs such as
DDR tuning, chip reset and CPU detection.

Signed-off-by: Wills Wang &lt;wills.wang@live.com&gt;
</content>
</entry>
<entry>
<title>MIPS: initial infrastructure for Microchip PIC32 architecture</title>
<updated>2016-02-01T21:14:00Z</updated>
<author>
<name>Purna Chandra Mandal</name>
<email>purna.mandal@microchip.com</email>
</author>
<published>2016-01-28T10:00:10Z</published>
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<id>urn:sha1:32c1a6eef8b467bb776f989caf0480fce6218598</id>
<content type='text'>
Create initial directory, Kconfigs needed for PIC32 architecture
support. Also add PIC32 specific register definition required for drivers.

Signed-off-by: Purna Chandra Mandal &lt;purna.mandal@microchip.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>MIPS: sync I/O related header files with linux-4.4</title>
<updated>2016-01-16T20:06:46Z</updated>
<author>
<name>Daniel Schwierzeck</name>
<email>daniel.schwierzeck@gmail.com</email>
</author>
<published>2016-01-12T20:48:25Z</published>
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<id>urn:sha1:23ff8633fd8ca75d2ffd4595b9c72bb1a5fdbd20</id>
<content type='text'>
Mainly sync asm/io.h to get a working ioremap() implementation
as well as the full set of I/O accessors. Pull in additional
header files to make this work.

Furthermore port over the directory 'arch/mips/include/asm/mach-generic/'
with contains default definitions for I/O and memory spaces and default
implementations for mapping those spaces. All files in that directory
can be overwritten by a SoC/machine.

Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
</entry>
<entry>
<title>MIPS: Kconfig: optimize gcc -march and -mtune setup</title>
<updated>2016-01-16T20:06:46Z</updated>
<author>
<name>Daniel Schwierzeck</name>
<email>daniel.schwierzeck@gmail.com</email>
</author>
<published>2015-12-26T18:55:37Z</published>
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<id>urn:sha1:0315a28909aa9781706bcd5743f2665220b6b099</id>
<content type='text'>
Move setup of -march to arch/mips/Makefile and follow the design on ARM.
Also add a possibility to chose specific CPU tune options.

Signed-off-by: Wills Wang &lt;wills.wang@live.com&gt;
Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
</entry>
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