u-boot.git/arch/mips/cpu/mips32/cache.S, branch master

MIPS: unify cache initialization code

2015-01-29T11:55:01+00:00

The mips32 & mips64 cache initialization code differs only in that the
mips32 code supports reading the cache size from coprocessor 0 registers
at runtime. Move the more developed mips32 version to a common
arch/mips/lib/cache_init.S & remove the now-redundant mips64 version in
order to reduce duplication. The temporary registers used are shuffled
slightly in order to work for both mips32 & mips64 builds. The RA
register is defined differently to suit mips32 & mips64, but will be
removed by a later commit in the series after further cleanup.

Signed-off-by: Paul Burton 
Cc: Daniel Schwierzeck

MIPS: avoid .set ISA for cache operations

2015-01-29T11:55:00+00:00

As a step towards unifying the cache maintenance code for mips32 &
mips64 CPUs, stop using ".set " directives in the more developed
mips32 version of the code. Instead, when present make use of the GCC
builtin for emitting a cache instruction. When not present, simply don't
bother with the .set directives since U-boot always builds with
-march=mips32 or higher anyway.

Signed-off-by: Paul Burton 
Cc: Daniel Schwierzeck

mips32: detect L1 cache sizes if they're not defined

2013-11-09T16:21:01+00:00

For boards such as the MIPS Malta with an FPGA core card it is desirable
to be able to detect the L1 cache sizes at runtime, since they are not
dependant upon the board but on the FPGA bitstream in use. This patch
performs that detection when the CONFIG_SYS_[DI]CACHE_SIZE macros are
not defined by the board configuration. In cases where the sizes are
detected this patch also removes the restriction that the I-cache &
D-cache line sizes must be the same, as this is not necessarily true.

If the cache sizes are defined by a configuration then they will be
hardcoded as before, so this patch will not add overhead to such
boards.

Signed-off-by: Paul Burton

MIPS: mips32/cache.S: use v1 register for indirect function calls

2013-07-24T13:51:07+00:00

Synchronize the code with mips64/cache.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos 
Cc: Daniel Schwierzeck

MIPS: mips32/cache.S: store cache line size in t8 register

2013-07-24T13:51:07+00:00

Synchronize the code with mips64/cache.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos 
Cc: Daniel Schwierzeck

MIPS: mips32/cache.S: save return address in t9 register

2013-07-24T13:51:06+00:00

Synchronize the code with mips64/cache.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos 
Cc: Daniel Schwierzeck

MIPS: mips32/cache.S: remove superfluous register assignment

2013-07-24T13:51:05+00:00

The t4 register already holds the cache
line size, and the value of the register
is not changed in mips_init_icache.

Get the cache line size value from t4 for
mips_init_dcache as well and remove the
superfluous assignment of t5 register.

Signed-off-by: Gabor Juhos

Add GPL-2.0+ SPDX-License-Identifier to source files

2013-07-24T13:44:38+00:00

Signed-off-by: Wolfgang Denk 
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini

MIPS: don't use camel-case style

2012-10-16T13:02:08+00:00

Replace camel-case style with upper-case style globally.

Signed-off-by: Zhizhou Zhang

MIPS: fix inconsistency in config option for cache operation mode

2012-04-02T13:54:53+00:00

Commit ab2a98b11716364bc5a8c43cdfa7fee176cda1d8 missed to
use the new config option in dcache_enable().

Fix this to avoid inconsistencies if someone wants to disable
and enable D-caches.

Signed-off-by: Daniel Schwierzeck