u-boot.git/arch/mips/cpu/mips32/cache.S, branch v2014.01

mips32: detect L1 cache sizes if they're not defined

2013-11-09T16:21:01Z

For boards such as the MIPS Malta with an FPGA core card it is desirable to be able to detect the L1 cache sizes at runtime, since they are not dependant upon the board but on the FPGA bitstream in use. This patch performs that detection when the CONFIG_SYS_[DI]CACHE_SIZE macros are not defined by the board configuration. In cases where the sizes are detected this patch also removes the restriction that the I-cache & D-cache line sizes must be the same, as this is not necessarily true. If the cache sizes are defined by a configuration then they will be hardcoded as before, so this patch will not add overhead to such boards. Signed-off-by: Paul Burton

MIPS: mips32/cache.S: use v1 register for indirect function calls

2013-07-24T13:51:07Z

Synchronize the code with mips64/cache.S, in order to allow further unifications. Signed-off-by: Gabor Juhos Cc: Daniel Schwierzeck

MIPS: mips32/cache.S: store cache line size in t8 register

2013-07-24T13:51:07Z

Synchronize the code with mips64/cache.S, in order to allow further unifications. Signed-off-by: Gabor Juhos Cc: Daniel Schwierzeck

MIPS: mips32/cache.S: save return address in t9 register

2013-07-24T13:51:06Z

Synchronize the code with mips64/cache.S, in order to allow further unifications. Signed-off-by: Gabor Juhos Cc: Daniel Schwierzeck

MIPS: mips32/cache.S: remove superfluous register assignment

2013-07-24T13:51:05Z

The t4 register already holds the cache line size, and the value of the register is not changed in mips_init_icache. Get the cache line size value from t4 for mips_init_dcache as well and remove the superfluous assignment of t5 register. Signed-off-by: Gabor Juhos

Add GPL-2.0+ SPDX-License-Identifier to source files

2013-07-24T13:44:38Z

Signed-off-by: Wolfgang Denk [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini

MIPS: don't use camel-case style

2012-10-16T13:02:08Z

Replace camel-case style with upper-case style globally. Signed-off-by: Zhizhou Zhang

MIPS: fix inconsistency in config option for cache operation mode

2012-04-02T13:54:53Z

Commit ab2a98b11716364bc5a8c43cdfa7fee176cda1d8 missed to use the new config option in dcache_enable(). Fix this to avoid inconsistencies if someone wants to disable and enable D-caches. Signed-off-by: Daniel Schwierzeck

MIPS: Coding style cleanups on common assembly files

2011-05-06T15:18:13Z

Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi

MIPS: Remove mips_cache_lock() feature

2011-05-06T15:18:13Z

As requested in commit e1390801a3c1a2b6d12fa90be368efc19f5b9bfd ([MIPS] Request for the 'mips_cache_lock()' removal), such feature is no longer needed for current MIPS implementation of U-Boot, and no one in the tree uses it for years. Signed-off-by: Shinya Kuribayashi